REV. B
AD8309
–16–
Slope and Intercept Adjustment
The AD8309 provides limited opportunities for adjustment of
its basic scaling parameters, which are controlled to within tight
limits through robust design. In applications involving the ob-
servation of measured signal levels on a DVM a slope of 10 mV
per decade is convenient: the reading is then directly in deci-
bels, needing only the positioning of the decimal point. This
may be simply achieved and at the same time trimmed to this
exact value using the scheme shown in Figure 35. A large filter
capacitor C
FILT
may be added as shown when the voltage is to
be measured on a DVM; this lowers the fluctuation in the lower-
order display digits.
A precision attenuator or signal generator is required to provide
several test levels at 10 dB intervals. The adjustment may also
made using an AM modulated signal, at about the center of the
dynamic range. For a modulation depth M, expressed as a
fraction, the decibel range between the peaks and troughs over
one cycle of the modulation period is given by
dB = 20 log
10
(1+M)/(1–M) (12)
For example, using an rms signal level of –40 dBm with a 70%
modulation depth (M = 0.7), the decibel range is 15 dB, as the
signal varies from –47.5 dBm to –32.5 dBm. The output would
thus be adjusted to have a peak-to-peak amplitude of 150 mV.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
10V
RSSI OUTPUT
10mV/dB 6 10%
10V
12
13
V
S
0.1mF 0.1mF
C
FILT
10mF
DVM
VR1
2kV
SLOPE
LIMITER
MAY BE
DISABLED
FOR RSSI
ONLY MODE
8.87kV
8.87kV
INPUT
COUPLING
Figure 35. Trimming Slope to 10 mV/dB
±
10%
The intercept can be adjusted by the use of the auxiliary circuit
shown in Figure 36, without changing the slope, which remains
20 mV/dB. This circuit provides a range of about ±4 dB on a
nominal intercept of –113 dBV (–100 dBm), with a fairly low
residual temperature sensitivity (+0.008 dB/°C). This is suffi-
cient to absorb the worst-case intercept error in the AD8309
plus system-level gain errors. VR2 is adjusted while applying an
accurately known CW signal near the lower end of the dynamic
range, in order to minimize the effect of any residual uncer-
tainty in the slope. For example, to position the intercept to
exactly –100 dBm, a test level of –60 dBm may be applied and
VR2 adjusted to produce a dc output of 40 dB above the inter-
cept, which is +0.8 V. This trim can optionally be combined
with the slope trim described above.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
0.1mF
10V
R
LIM
RSSI
0.1mF
10V
12
13
V
S
47kV
9.6kV
VR2
2kV
INTERCEPT
IN914
OR SIMILAR
Figure 36. Trimming Intercept to –113 dBV
±
4 dB
APPLICATIONS
The AD8309 is a versatile and easily applied log-limiting amp.
Being complete, it can be used with very few external compo-
nents, and most applications can be accommodated using the
simple connections shown in the preceding section. A few ex-
amples of more specialized applications are provided here.
Log Amp with High Slope Voltage
Where a higher RSSI slope voltage is required, and/or complete
calibration with good temperature stability and minimal interac-
tion between trims, the interface shown in Figure 37 may be
used. Note that at 50 mV/dB, the full 100 dB dynamic range of
the AD8309 requires a 5 V swing. This can be provided by a
single supply operational amplifier having a rail-to-rail output
stage and operating from a 6 V supply. Where a lower range is
sufficient, or when using the 40 mV/dB option, a 5 V supply will
be adequate.
In this application, the supply current into the VPS2 pin is only
slightly dependent on the current delivered to the load resis-
tance, R
L
, so a voltage dropping resistor, R
D
, may be added to
lower the supply to the AD8309, which can meet all of its speci-
fications with a 2.7 V supply. The lower chip dissipation and
the resulting reduction in operating temperature will minimize
degradation of noise figure at high ambient temperatures. R
D
is
calculated as follows:
R
V
mA
R
D
S
LIM
=
3
25
100
(13)
which allows for operation at ambient temperatures up to +85°C.
Table II may be used to select the component values for various
different operating conditions. The slope adjustment range is
±10% and the intercept adjustment range is ±3 dB. Since the
intercept offset bias is derived from the supply, there is a sensi-
tivity to this voltage. Where supply stability is poor, a regulator
may be needed to bias VR2 and R4.
REV. B
AD8309
–17–
Table II.
Slope Intercept R1 R2 R4 R5 V
OUT
(V) at
mV/dB dBV k k k k –88 dBV +12 dBV
40 –102 3.92 8.87 O/C 1 0.56 4.56
50 –103 1.05 9.53 O/C 1 0.75 5.75
40 –90 3.92 8.87 20.5 1.05 0.08 4.08
50 –90 1.05 9.53 15.4 1.07 0.1 5.10
Setting the Limiter Output Level
The limiter output is a pair of differential currents of magni-
tude, I
OUT
, from high␣ impedance (open-collector) sources.
These are converted to equal-amplitude voltages by supply-
referenced load resistors, R
LOAD
. The limiter output current is
set by R
LIM
, the resistor connected between Pin 9 (LMDR) and
ground depending on the application, the resulting voltage may
be used in a fully balanced or unbalanced manner. It is good
practice to retain the both resistors, whichever output mode is
used. The unbalanced, or single sided mode, is more inclined to
result in instabilities caused by the very high gain of the signal
path. If the limiter output is not needed, LMDR should be left
open with LMHI and LMLO being tied to VPS2.
The limiter output current is set by the equation:
I
OUT
= –400 mV/R
LIM
and has an absolute accuracy of ±5%.
The voltage on each of the limiter pins will be given by:
V
LIM
= V
S
– 400 mV × R
LOAD
/R
LIM
The limiter current may be set as high as 10 mA, which requires
R
LIM
to be 40 ohms, and can be optionally increased somewhat
beyond this level. It is inadvisable, however, to use high bias
currents, since the gain of this wide bandwidth signal path is
proportional to it, and the risk of instability is elevated as R
LIM
is
reduced (recommended value is 400 ).
The limiter output is specified for input levels between –78 dBV
and +9 dBV. The output of the limiter will be unstable for levels
below –78 dBV (–65 dBm).
High Output Limiter Loading
The AD8309 can generate a fairly large output power at its
differential limiter output interface. This may be coupled into a
50 grounded load using the narrow-band coupling network
following similar lines to those provided for input matching.
Alternatively, a flux-linked transformer, having a center-tapped
primary, may be used. Even higher output powers can be ob-
tained using emitter-followers. In Figure 38, the supply voltage
to the AD8309 is dropped from 5 V to about 4.2 V, by the
diode. This increases the available swing at each output to about
2 V. Taking both outputs differentially, a square wave output of
4 V p-p can be generated.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
0.1mF
10V
R
LIM
RSSI
3V TO 5V
0.1mF
10V
12
13
+5V
IN914
APPROX. 4.2V
R
LOAD
SET R
L
= 5*R
LIM
5V TO 3V
DIFFERENTIAL
OUTPUT = 4V pk-pk
R
LOAD
Figure 38. Increasing Limiter Output Voltage
When operating at high output power levels and high frequen-
cies, very careful attention must be paid to the issue of stability.
Oscillation is likely to be observed when the input signal level is
low, due to the extremely high gain-bandwidth product of the
AD8309 under such conditions. These oscillations will be less
evident when signal-balancing networks are used, operating at
frequencies below 200 MHz, and they will generally be fully
quenched by the signal at input levels of a few dB above the
noise floor.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
10V
10V
12
13
V
S
0.1mF
0.1mF
VR2
10kV
INT
INPUT
R1
R2
VR1
2kV
SLOPE
R3
33.2kV
R5
R4
R6
1.96kV
AD8031
GND
RSSI
AD8309 SUPPLY DROPPED TO 3V R
D
= (V
S
–3V)/25mA
0.1mF
Figure 37. Buffered RSSI Output with Slope and Intercept Adjustments
REV. B
AD8309
–18–
Modulated Limiter Output
The limiter output stage of the AD8309 also provides an analog
multiplication capability: the amplitude of the output square
wave can be controlled by the current withdrawn from LMDR
(Pin 9). An analog control input of 0 V to +1 V is used to gener-
ate an exactly-proportional current of 0 mA to 10 mA in the npn
transistor, whose collector is held at a fixed voltage of 400 mV
by the internal bias in the AD8309. When the input signal is
above the limiting threshold, the output will then be a square-
wave whose amplitude is proportional to the control bias.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
10V
10V
12
13
V
S
1.8kV
AD8031
0.1mF
RSSI
0.1mF
VARIABLE
OUTPUT
8.2kV
0V TO +1V
18V
0mA TO
10mA
2N3904
0.1mF
Figure 39. Variable Limiter Output Programming
Effect of Waveform Type on Intercept
The AD8309 fundamentally responds to voltage and not to
power. A direct consequence of this characteristic is that input
signals of equal rms power, but differing crest factors, will pro-
duce different results at the log amp’s output.
The effect of differing signal waveforms is to shift the effective
value of the log amp’s intercept. Graphically, this looks like a
vertical shift in the log amp’s transfer function. The device’s
logarithmic slope however is not affected. For example, consider
the case of the AD8309 being alternately fed by an unmodu-
lated sine wave and by a single CDMA channel of the same rms
power. The AD8309’s output voltage will differ by the equiva-
lent of 3.55 dB (71 mV) over the complete dynamic range of the
device (the output for a CDMA input being lower).
Table III shows the correction factors that should be applied to
measure the rms signal strength of a various signal types. A sine
wave input is used as a reference. To measure the rms power of
a square wave, for example, the mV equivalent of the dB value
given in the table (20 mV/dB times 3.01 dB) should be sub-
tracted from the output voltage of the AD8309.
Table III. Shift in AD8309 Output for Signals with Differing
Crest Factors
Correction Factor
Signal Type (Add to Output Reading)
Sine Wave 0 dB
Square Wave or DC –3.01 dB
Triangular Wave +0.9 dB
GSM Channel (All Time Slots On) +0.55 dB
CDMA Channel +3.55 dB
PDC Channel (All Time Slots On) +0.58 dB
Gaussian Noise +2.51 dB
Evaluation Board
An evaluation board, carefully laid out and tested to demon-
strate the specified high speed performance of the AD8309 is
available. Figure 40 shows the schematic of the evaluation board
which fairly closely follows the basic connections schematic
shown in Figure 30. For ordering information, please refer to
the Ordering Guide. Links, switches and component settings for
different setups are described in Table IV.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
12
13
C3
0.1mF
R/L
52.3V
C1
0.01mF
C2
0.01mF
R2
4.7V
R1
0V
+V
S
EXT
ENABLE
C7 (OPEN)
R6
402V
C4
0.1mF
R7
402V
R3
0V
R5
4.7V
R4
(OPEN)
V
RSSI
+V
S
L1
(OPEN)
C5
0.01mF
LMHI
C6
0.01mF
LMLO
LK1
R8
402V
SIG
INHI
SIG
INLO
A
B
Figure 40. Evaluation Board Schematic

AD8309ARUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers 5-500 MHz 100 dB w/ Limiter Output
Lifecycle:
New from this manufacturer.
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