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AD8309ARUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REV. B
AD8309
–13–
Because of the very high gain bandwidth product of this ampli-
fier considerable care must be exercised in using the limiter
outputs. The minimum necessary bias current and voltage
swings should be used. These outputs are best utilized in a fully-
differential mode. A flux-coupled transformer, a balun, or an
output matching network can be selected to transform these
voltages to a single-sided form. Equal load resistors are recom-
mended, even when only one output pin is used, and these
should always be returned to the same well decoupled node on
the PC board. When the AD8309 is used only to generate an
RSSI output, the limiter should be completely disabled by omit-
ting R
LIM
and strapping LMHI and LMLO to VPS2.
OA
VPS2 LMHI LMLO
COM1
LMDR
R
LIM
2.6kV
1.3kV1.3kV
Q1
4e
Q2
4e
Q3
1.3kV1.3kV
FROM FINAL
LIMITER STAGE
400mV
ZERO-TC
Figure 28. Limiter Output Interface
RSSI Output Interface
The outputs from the ten detectors are differential currents,
having an average value that is dependent on the signal input
level, plus a fluctuation at twice the input frequency. The cur-
rents are summed at the internal nodes LGP and LGN shown in
Figure 29. A further current I
TC
is added to LGP, to position
the intercept to –108 dBV, by raising the RSSI output voltage
for zero input, and to provide temperature compensation , re-
sulting in a stable intercept. For zero signal conditions, all the
detector output currents are equal. For a finite input, of either
polarity, their difference is converted by the output interface to
a single-sided voltage nominally scaled 20 mV/dB (400 mV per
decade), at the output VLOG (Pin 16). This scaling is con-
trolled by a separate feedback stage, having a tightly controlled
transconductance. A small uncertainty in the log slope and
intercept remains (see Specifications); the intercept may be
adjusted (see Applications).
VPS2
FLTR
VLOG
20mV/dB
COMM
I
SOURCE
>50mA
ON DEMAND
C1
3.5pF
CURRENT
MIRROR
I
SINK
FIXED
1mA
3.3kV3.3kV
125mA
1.3kV1.3kV
V
LOG
TRANSCONDUCTANCE
DETERMINES SLOPE
I
T
LGP
LGN
SUMMED
DETECTOR
OUTPUTS
C
F
250ms
Figure 29. Simplified RSSI Output Interface
The RSSI output bandwidth, f
LP
, is nominally 3.5 MHz. This is
controlled by the compensation capacitor C1, which may be
increased by adding an external capacitor, C
F
, between FLTR
(Pin 10) and VLOG (Pin 16). An external 33 pF will reduce f
LP
to 350 kHz, while 360 pF will set it to 35 kHz, in each case with
an essentially one-pole response. In general, the relationships
are:
C
f
pF f
CpF
F
LP
LP
F
=
×
=
×
+
−
12 7 10
35
12 7 10
35
10 6
.
–. ;
.
.
–
(7)
Using a load resistance of 50 Ω or greater, and at any tempera-
ture, the peak output voltage may be at least 2.4 V when using a
supply of 4.5 V, and at least 2.1 V for a 3 V supply, which are
consistent with the maximum permissible input levels. The incre-
mental output resistance is approximately 0.3 Ω at low frequen-
cies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies.
The output is unconditionally stable with load capacitance, but
it should be noted while the peak sourcing current is over 100 mA,
and able to rapidly charge even large capacitances, the internally
provided sinking current is only 1 mA. Thus, the fall time from
the 2 V level will be as long as 2 µs for a 1 nF load. This may be
reduced by adding a grounded load resistance.
USING THE AD8309
The AD8309 exhibits very high gain from 1 MHz to over 1 GHz,
at which frequency the gain of the main path is still over 65 dB.
Consequently, it is susceptible to all signals within this very
broad frequency range which find their way to the input termi-
nals. It is important to remember that these are quite indistin-
guishable from the “wanted” signal, and will have the effect of
raising the apparent noise floor (that is, lowering the useful
dynamic range). Therefore, while the signal of interest may be
an IF of, say, 200 MHz, any of the following could easily be
larger than this signal at the lower extremities of its dynamic
range: a 60 Hz hum, picked up due to poor grounding tech-
niques; spurious coupling from digital logic on the same PC
board; a strong EMI source; etc.
Very careful shielding is essential to guard against such un-
wanted signals, and also to minimize the likelihood of instability
due to HF feedback from the limiter outputs to the input. With
this in mind, the minimum possible limiter gain should be used.
Where only the logarithmic amplifier (RSSI) function is re-
quired, the limiter should be disabled by omitting R
LIM
and
tying the outputs LMHI and LMLO directly to VPS2.
A good ground plane should be used to provide a low imped-
ance connection to the common pins, for the decoupling
capacitor(s) used at VPS1 and VPS2, and at the output ground.
It is inadvisable to assume that any ground plane is an equipo-
tential, however, and neither of the signal inputs should be ac-
coupled directly to it, but kept separate, being returned instead
to the “low” associated with the source. This requires isolating
the “low”’ side of an input connector with a small resistance to
the ground plane. Note that COM2 is a special ground pin
serving just the RSSI output.
The voltages at the two supply pins should not be allowed to
differ greatly; up to 500 mV is permissible It is desirable to
allow VPS1 to be slightly more negative than VPS2. When the
primary supply is greater than 2.7 V, the decoupling resistors R1
and R2 may be increased to improve the isolation and lower
dissipation in the IC. However, since VPS2 supports the RSSI
REV. B
AD8309
–14–
load current, which may be large, the value of R2 should take
this into account.
The four pins labeled PADL tie down directly to the metallic
lead frame, and are thus connected to the back of the chip. The
process on which the AD8309 is fabricated uses a bonded-wafer
technique to provide a silicon-on-insulator isolation, and there is
no junction or other dc path from the back side to the circuitry
on the surface. These paddle pins must be connected directly to
the ground plane using the shortest possible lead lengths to
minimize inductance.
Basic Connections
Figure 30 shows the connections required for most applications.
The inputs are ac-coupled by C1 and C2, which normally
should have the same value, say, C
O
. The coupling time con-
stant is R
O
C
O
/2, where R
O
= R
S
+ R
IN
, thus forming a high pass
corner with a 3 dB attenuation at f
HP
= 1/(π R
T
C
C
). In high-
frequency applications, f
HP
should be chosen as large as pos-
sible, to minimize the coupling of unwanted signals. On the
other hand, in low frequency applications, a simple RC network
forming a low-pass filter should be added at the input for the
same reason.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
0.1mF
R2
10V
R
LOAD
R
LOAD
NC
R
LIM
RSSI
LMHI
LMLO
0.1mF
R1
10V
ENABLE
R
T
C1
C2
SEE TEXT FOR MORE
ABOUT DECOUPLING
SIGNAL
INPUTS
52.3V
4.7nH
FOR BROADBAND 50V
TERMINATION TO 1GHz
NC = NO CONNECT
12
13
V
S
Figure 30. Basic Connections
Where it is necessary to terminate the source at a low imped-
ance, the resistor R
T
should be added, with allowance for the
shunting effect of the 1 kΩ input resistance (R
IN
) of the AD8309.
For example, to terminate a 50 Ω source, a 52.3 Ω␣ resistor
should be used for signal frequencies up to about 50 MHz. The
termination means may be placed either at the input or at the
log amp side of the coupling capacitors. In the former case
smaller capacitors can be used for a given frequency range; in
the latter case, the dc resistance is lowered directly at the log
amp inputs, which helps to keep offsets to a minimum. At
higher frequencies, the reactance of the 2.5 pF input capaci-
tance must be accounted for. A 4.7 nH inductor in series with
the 52.3 Ω termination resistor provides an essentially flat 50 Ω
input impedance to 1 GHz. An impedance-transforming net-
work is preferably used to provide a 50 Ω interface, since this
also introduces a balanced voltage gain of typically 13 dB and
the AD8309 has a very high capacity for large input voltages.
Figure 31 shows the output versus the input level, with the axis
marked in dBm (correct only when terminated in 50 Ω), for sine
inputs at 5 MHz, 50 MHz, 100 MHz and 200 MHz. Figure 32
shows the typical logarithmic linearity (law conformance) under
the same conditions.
INPUT LEVEL – dBm Re 50V
2.5
–100
RSSI OUTPUT – V
2.0
1.5
1.0
0.5
0
–80 –60 –40 –20 0 20 40
100MHz
50MHz
200MHz
5MHz
Figure 31. RSSI Output vs. Input Level at T
A
= +25
°
C, for
Frequencies of 5 MHz, 50 MHz, 100 MHz and 200 MHz
INPUT LEVEL – dBm Re 50V
5
–90
ERROR – dB
4
3
2
1
0
–1
–2
–3
–4
–5
–80 –70 –60 –50
–40 –30 –20 –10 0 10 20 30
DYNAMIC RANGE
5MHz
50MHz
100MHz
200MHz
3dB
93
99
103
102
1dB
85
91
97
96
50MHz
5MHz
200MHz
100MHz
Figure 32. Log Linearity vs. Input Level at T
A
= +25
°
C, for
Frequencies of 5 MHz, 50 MHz, 100 MHz and 200 MHz
Input Matching
Where either a higher sensitivity or a better high frequency
match is required, an input matching network is valuable. Using
a flux-coupled transformer to achieve the impedance transfor-
mation also eliminates the need for coupling capacitors, lowers
any dc offset voltages generated directly at the input, and use-
fully balances the drives to INHI and INLO, permitting full
utilization of the unusually large input voltage capacity of the
AD8309.
The choice of turns ratio will depend somewhat on the fre-
quency. At frequencies below 30 MHz, the reactance of the
input capacitance is much higher than the real part of the input
impedance. In this frequency range, a turns ratio of 2:9 will
lower the effective input impedance to 50 Ω while raising the
input voltage by 13 dB. However, this does not lower the effect
of the short circuit noise voltage by the same factor, since there
will be a contribution from the input noise current. Thus, the
total noise will be reduced by a smaller factor. The intercept at
the primary input will be lowered to –120 dBV (–107 dBm).
Impedance matching and drive balancing using a flux-coupled
transformer is useful whenever broadband coupling is required.
However, this may not always be convenient. At high frequen-
cies, it will often be preferable to use a narrow-band matching
network, as shown in Figure 33, which has several advantages.
First, the same voltage gain can be achieved, providing increased
REV. B
AD8309
–15–
sensitivity, but now a measure of selectively is simultaneously
introduced. Second, the component count is low: two capacitors
and an inexpensive chip inductor are needed. Third, the net-
work also serves as a balun. Analysis of this network shows that
the amplitude of the voltages at INHI and INLO are quite simi-
lar when the impedance ratio is fairly high (say, 50 Ω to 1000 Ω).
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
0.1mF
10V
NC
R
LIM
RSSI
LIMITER
OUTPUT
0.1mF
10V
C2 = C
M
Z
IN
NC = NO CONNECT
12
13
V
S
C1 = C
M
L
M
Figure 33. High Frequency Input Matching Network
Figure 34 shows the response for a center frequency of 100 MHz.
The response is down by 50 dB at one-tenth the center frequency,
falling by 40 dB per decade below this. The very high frequency
attenuation is relatively small, however, since in the limiting
case it is determined simply by the ratio of the AD8309’s input
capacitance to the coupling capacitors. Table I provides solu-
tions for a variety of center frequencies f
C
and matching from
impedances Z
IN
of nominally 50 Ω and 100 Ω. Exact values are
shown, and some judgment is needed in utilizing the nearest
standard values.
Table I.
Match to 50 ⍀ Match to 100 ⍀
(Gain = 13 dB) (Gain = 10 dB)
f
C
C
M
L
M
C
M
L
M
MHz pF nH pF nH
10 140 3500 100.7 4790
10.7 133 3200 94.1 4460
15 95.0 2250 67.1 3120
20 71.0 1660 50.3 2290
21.4 66.5 1550 47.0 2120
25 57.0 1310 40.3 1790
30 47.5 1070 33.5 1460
35 40.7 904 28.8 1220
40 35.6 779 25.2 1047
45 31.6 682 22.4 912
50 28.5 604 20.1 804
60 23.7 489 16.8 644
80 17.8 346 12.6 448
100 14.2 262 10.1 335
120 11.9 208 8.4 261
150 9.5 155 6.7 191
200 7.1 104 5.03 125
250 5.7 75.3 4.03 89.1
300 4.75 57.4 3.36 66.8
350 4.07 45.3 2.87 52.1
400 3.57 36.7 2.52 41.8
450 3.16 30.4 2.24 34.3
500 2.85 25.6 2.01 28.6
FREQUENCY – MHz
14
60
DECIBELS
13
12
11
10
9
8
7
6
5
70 80 90 100 110 120 130
4
3
2
1
0
–1
140 150
GAIN
INPUT AT
TERMINATION
Figure 34. Response of 100 MHz Matching Network
General Matching Procedure
For other center frequencies and source impedances, the following
method can be used to calculate the basic matching parameters.
Step 1: Tune Out C
IN
At a center frequency f
C
, the shunt impedance of the input
capacitance C
IN
can be made to disappear by resonating with a
temporary inductor L
IN
, whose value is given by
L
IN
= 1/{(2
π
f
C
)
2
C
IN
} = 10
10
/f
C
2
(8)
when C
IN
= 2.5 pF. For example, at f
C
= 100 MHz, L
IN
= 1 µH.
Step 2: Calculate C
O
and L
O
Now having a purely resistive input impedance, we can calculate
the nominal coupling elements C
O
and L
O
, using
C
fRR
L
RR
f
O
CINM
O
IN M
C
=
()
=
()
1
2
2
π
π
;
(9)
For the AD8309, R
IN
is 1 kΩ. Thus, if a match to 50 Ω is
needed, at f
C
= 100 MHz, C
O
must be 7.12 pF and L
O
must be
356 nH.
Step 3: Split C
O
Into Two Parts
Since we wish to provide the fully-balanced form of network
shown in Figure 33, two capacitors C1 = C2
each of nominally
twice C
O
, shown as C
M
in the figure, can be used. This requires
a value of 14.24 pF in this example. Under these conditions, the
voltage amplitudes at INHI and INLO will be similar. A some-
what better balance in the two drives may be achieved when C1
is made slightly larger than C2, which also allows a wider range
of choices in selecting from standard values. For example, ca-
pacitors of C1 = 15 pF and C2 = 13 pF may be used (making
C
O
= 6.96 pF).
Step 4: Calculate L
M
The matching inductor required to provide both L
IN
and L
O
is
just the parallel combination of these:
L
M
= L
IN
L
O
/(L
IN
+ L
O
) (10)
With L
IN
= 1 µH and L
O
= 356 nH, the value of L
M
to complete
this example of a match of 50 Ω at 100 MHz is 262.5 nH. The
nearest standard value of 270 nH may be used with only a slight
loss of matching accuracy. The voltage gain at resonance de-
pends only on the ratio of impedances, as is given by
GAIN
R
R
R
R
IN
S
IN
S
=
=
20 10log log
(11)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD8309ARUZ

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Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers 5-500 MHz 100 dB w/ Limiter Output
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