MR2A16A Data Sheet, Rev. 6
14 Freescale Semiconductor
Timing Specifications
Table 12. Write Cycle Timing 3 (LB/UB Controlled)
1, 2, 3, 4, 5, 6
Parameter Symbol Min Max Unit
Write cycle time
7
t
AVAV
35 — ns
Address set-up time t
AVBL
0—ns
Address valid to end of write (G
high) t
AVBH
18 — ns
Address valid to end of write (G
low) t
AVBH
20 — ns
Byte pulse width (G
high)
t
BLEH
t
BLWH
15 — ns
Byte pulse width (G
low)
t
BLEH
t
BLWH
15 — ns
Data valid to end of write t
DVBH
10 — ns
Data hold time t
BHDX
0—ns
Write recovery time t
BHAX
12 — ns
NOTES:
1
A write occurs during the overlap of E low and W low.
2
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
3
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
4
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
5
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
6
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
7
All write cycle timings are referenced from the last valid address to the first transition address.
