MR2A16A Data Sheet, Rev. 6
8 Freescale Semiconductor
Timing Specifications
Timing Specifications
Read Mode
Table 9. Read Cycle Timing
1, 2
Parameter Symbol Min Max Unit
Read cycle time t
AVAV
35 — ns
Address access time t
AVQV
—35ns
Enable access time
3
t
ELQV
—35ns
Output enable access time t
GLQV
—15ns
Byte enable access time t
BLQV
—15ns
Output hold from address change t
AXQX
3—ns
Enable low to output active
4, 5
t
ELQX
3—ns
Output enable low to output active
4, 5
t
GLQX
0—ns
Byte enable low to output active
4, 5
t
BLQX
0—ns
Enable high to output Hi-Z
4, 5
t
EHQZ
015ns
Output enable high to output Hi-Z
4, 5
t
GHQZ
010ns
Byte high to output Hi-Z
4, 5
t
BHQZ
010ns
NOTES:
1
W is high for read cycle.
2
Due to product sensitivities to noise, power supplies must be properly grounded and
decoupled, and bus contention conditions must be minimized or eliminated during read and
write cycles.
3
Addresses valid before or at the same time E goes low.
4
This parameter is sampled and not 100% tested.
5
Transition is measured ±200 mV from steady-state voltage.
