2000 Jan 04 20
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.3.9.1 Acceptance Code Register (ACR)
Table 8 ACR bit allocation; can address 4
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AC.7 AC.6 AC.5 AC.4 AC.3 AC.2 AC.1 AC.0
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). When a message is
received which passes the acceptance test and there is
receive buffer space left, then the respective descriptor
and data field are sequentially stored in the RXFIFO.
When the complete message has been correctly received
the following occurs:
• The receive status bit is set HIGH (full)
• If the receive interrupt enable bit is set HIGH (enabled),
the receive interrupt is set HIGH (set).
The acceptance code bits (AC.7 to AC.0) and the eight
most significant bits of the message’s identifier
(ID.10 to ID.3) must be equal to those bit positions which
are marked relevant by the acceptance mask bits
(AM.7 to AM.0). If the conditions as described in the
following equation are fulfilled, acceptance is given:
(ID.10 to ID.3) ≡ (AC.7 to AC.0)] ∨ (AM.7 to AM.0)
≡ 11111111
6.3.9.2 Acceptance Mask Register (AMR)
Table 9 AMR bit allocation; CAN address 5
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AM.7 AM.6 AM.5 AM.4 AM.3 AM.2 AM.1 AM.0
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). The acceptance mask
register qualifies which of the corresponding bits of the
acceptance code are ‘relevant’ (AM.X = 0) or ‘don’t care’
(AM.X = 1) for acceptance filtering.
6.3.9.3 Other registers
The other registers are described in Section 6.5.
6.4 PeliCAN mode
6.4.1 PELICAN ADDRESS LAYOUT
The CAN controller’s internal registers appear to the CPU
as on-chip memory mapped peripheral registers. Because
the CAN controller can operate in different modes
(operating/reset; see also Section 6.4.3), one has to
distinguish between different internal address definitions.
Starting from CAN address 32 the complete internal RAM
(80-byte) is mapped to the CPU interface.
