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SJA1000T/N1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68
2000 Jan 04 22
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes
1. It should be noted that the registers are repeated within higher CAN address areas (the most significant bit of the
8-bit CPU address is not decoded: CAN address 128 continues with CAN address 0 and so on).
2. Test register is used for production testing only. Using this register during normal operation may result in undesired
behaviour of the device.
3. SFF = Standard Frame Format.
4. EFF = Extended Frame Format.
5. These address allocations reflect the FIFO RAM space behind the current message. The contents are random after
power-up and contain the beginning of the next message which is received after the current one. If no further
message is received, parts of old messages may occur here.
6. Some bits are writeable in reset mode only (CAN mode, CBP, RXINTEN and clock off).
27 (FIFO RAM);
note 5
RX data 7 − TX data 7 reserved (00H) −
28 (FIFO RAM);
note 5
RX data 8 − TX data 8 reserved (00H) −
29 RX message counter − RX message
counter
−
30 RX buffer start address − RX buffer start
address
RX buffer start
address
31 clock divider clock divider; note 6 clock divider clock divider
32 internal RAM address 0 (FIFO) − internal RAM
address 0
internal RAM
address 0
33 internal RAM address 1 (FIFO) − internal RAM
address 1
internal RAM
address 1
↓↓ ↓ ↓ ↓
95 internal RAM address 63
(FIFO)
− internal RAM
address 63
internal RAM
address 63
96 internal RAM address 64
(TX buffer)
− internal RAM
address 64
internal RAM
address 64
↓↓ ↓ ↓ ↓
108 internal RAM address 76
(TX buffer)
− internal RAM
address 76
internal RAM
address 76
109 internal RAM address 77 (free) − internal RAM
address 77
internal RAM
address 77
110 internal RAM address 78 (free) − internal RAM
address 78
internal RAM
address 78
111 internal RAM address 79 (free) − internal RAM
address 79
internal RAM
address 79
112 (00H) − (00H) −
↓↓ ↓ ↓ ↓
127 (00H) − (00H) −
CAN
ADDRESS
OPERATING MODE RESET MODE
READ WRITE READ WRITE
2000 Jan 04 23
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.2 RESET VALUES
Detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the
reset mode. On the ‘1-to-0’ transition of the reset mode bit, the CAN controller returns to the mode defined within the
mode register.
Table 11 Reset mode configuration; notes 1 and 2
REGISTER BIT SYMBOL NAME
VALUE
RESET BY
HARDWARE
SETTING MOD.0
BY SOFTWARE
OR DUE TO
BUS-OFF
Mode MOD.7 to 5 − reserved 0 (reserved) 0 (reserved)
MOD.4 SM Sleep Mode 0 (wake-up) 0 (wake-up)
MOD.3 AFM Acceptance Filter Mode 0 (dual) X
MOD.2 STM Self Test Mode 0 (normal) X
MOD.1 LOM Listen Only Mode 0 (normal) X
MOD.0 RM Reset Mode 1 (present) 1 (present)
Command CMR.7 to 5 − reserved 0 (reserved) 0 (reserved)
CMR.4 SRR Self Reception Request 0 (absent) 0 (absent)
CMR.3 CDO Clear Data Overrun 0 (no action) 0 (no action)
CMR.2 RRB Release Receive Buffer 0 (no action) 0 (no action)
CMR.1 AT Abort Transmission 0 (absent) 0 (absent)
CMR.0 TR Transmission Request 0 (absent) 0 (absent)
Status SR.7 BS Bus Status 0 (bus-on) X
SR.6 ES Error Status 0 (ok) X
SR.5 TS Transmit Status 1 (wait idle) 1 (wait idle)
SR.4 RS Receive Status 1 (wait idle) 1 (wait idle)
SR.3 TCS Transmission Complete
Status
1 (complete) X
SR.2 TBS Transmit Buffer Status 1 (released) 1 (released)
SR.1 DOS Data Overrun Status 0 (absent) 0 (absent)
SR.0 RBS Receive Buffer Status 0 (empty) 0 (empty)
Interrupt IR.7 BEI Bus Error Interrupt 0 (reset) 0 (reset)
IR.6 ALI Arbitration Lost Interrupt 0 (reset) 0 (reset)
IR.5 EPI Error Passive Interrupt 0 (reset) 0 (reset)
IR.4 WUI Wake-Up Interrupt 0 (reset) 0 (reset)
IR.3 DOI Data Overrun Interrupt 0 (reset) 0 (reset)
IR.2 EI Error Warning Interrupt 0 (reset) X; note 3
IR.1 TI Transmit Interrupt 0 (reset) 0 (reset)
IR.0 RI Receive Interrupt 0 (reset) 0 (reset)
2000 Jan 04 24
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Interrupt
enable
IER.7 BEIE Bus Error Interrupt
Enable
XX
IER.6 ALIE Arbitration Lost Interrupt
Enable
XX
IER.5 EPIE Error Passive Interrupt
Enable
XX
IER.4 WUIE Wake-Up Interrupt
Enable
XX
IER.3 DOIE Data Overrun Interrupt
Enable
XX
IER.2 EIE Error Warning Interrupt
Enable
XX
IER.1 TIE Transmit Interrupt
Enable
XX
IER.0 RIE Receive Interrupt Enable X X
Bus timing 0 BTR0.7 SJW.1 Synchronization Jump
Width 1
XX
BTR0.6 SJW.0 Synchronization Jump
Width 0
XX
BTR0.5 BRP.5 Baud Rate Prescaler 5 X X
BTR0.4 BRP.4 Baud Rate Prescaler 4 X X
BTR0.3 BRP.3 Baud Rate Prescaler 3 X X
BTR0.2 BRP.2 Baud Rate Prescaler 2 X X
BTR0.1 BRP.1 Baud Rate Prescaler 1 X X
BTR0.0 BRP.0 Baud Rate Prescaler 0 X X
Bus timing 1 BTR1.7 SAM Sampling X X
BTR1.6 TSEG2.2 Time Segment 2.2 X X
BTR1.5 TSEG2.1 Time Segment 2.1 X X
BTR1.4 TSEG2.0 Time Segment 2.0 X X
BTR1.3 TSEG1.3 Time Segment 1.3 X X
BTR1.2 TSEG1.2 Time Segment 1.2 X X
BTR1.1 TSEG1.1 Time Segment 1.1 X X
BTR1.0 TSEG1.0 Time Segment 1.0 X X
REGISTER BIT SYMBOL NAME
VALUE
RESET BY
HARDWARE
SETTING MOD.0
BY SOFTWARE
OR DUE TO
BUS-OFF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68

SJA1000T/N1,112

Mfr. #:
Buy SJA1000T/N1,112
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC STAND-ALONE CAN CONTROLLER
Lifecycle:
New from this manufacturer.
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