2000 Jan 04 55
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Table 48 Output pin configuration; note 1
Notes
1. X = don’t care.
2. TPX is the on-chip output transistor X, connected to V
DD
.
3. TNX is the on-chip output transistor X, connected to V
SS
.
4. TXX is the serial output level on pin TX0 or TX1. It is required that the output level on the CAN-bus line is dominant
when TXD = 0 and recessive when TXD = 1.
DRIVE TXD OCTPX OCTNX OCPOLX TPX
(2)
TNX
(3)
TXX
(4)
Float X 0 0 X off off float
Pull-down 0 0 1 0 off on LOW
1 0 1 0 off off float
0 0 1 1 off off float
1 0 1 1 off on LOW
Pull-up 0 1 0 0 off off float
1 1 0 0 on off HIGH
0 1 0 1 on off HIGH
1 1 0 1 off off float
Push-pull 0 1 1 0 off on LOW
1 1 1 0 on off HIGH
0 1 1 1 on off HIGH
1 1 1 1 off on LOW
The bit sequence (TXD) is sent via TX0 and TX1.
The voltage levels on the output driver pins depends on
both the driver characteristics programmed by OCTP,
OCTN (float, pull-up, pull-down, push-pull) and the output
polarity programmed by OCPOL.
6.5.4 CLOCK DIVIDER REGISTER (CDR)
The clock divider register controls the CLKOUT frequency
for the microcontroller and allows to deactivate the
CLKOUT pin. Additionally a dedicated receive interrupt
pulse on TX1, a receive comparator bypass and the
selection between BasicCAN mode and PeliCAN mode is
made here. The default state of the register after hardware
reset is divide-by-12 for Motorola mode (00000101) and
divide-by-2 for Intel mode (00000000).
On software reset (reset request/reset mode) this register
is not influenced.
The reserved bit (CDR.4) will always reflect a logic 0.
The application software should always write a logic 0 to
this bit in order to be compatible with future features, which
may be 1-active using this bit.
Table 49 Bit interpretation of the clock divider register (CDR); CAN address 31
Note
1. This bit cannot be written. During read-out of this register always a zero is given.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CAN mode CBP RXINTEN (0)
(1)
clock off CD.2 CD.1 CD.0
2000 Jan 04 56
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.5.4.1 CD.2 to CD.0
The bits CD.2 to CD.0 are accessible without restrictions in reset mode as well as in operating mode. These bits are used
to define the frequency at the external CLKOUT pin. For an overview of selectable frequencies see Table 50.
Table 50 CLKOUT frequency selection; note 1
Note
1. f
osc
is the frequency of the external oscillator (XTAL).
CD.2 CD.1 CD.0 CLKOUT FREQUENCY
000
001
010
011
100
101
110
111f
osc
f
osc
2
--------
f
osc
4
--------
f
osc
6
--------
f
osc
8
--------
f
osc
10
--------
f
osc
12
--------
f
osc
14
--------
6.5.4.2 Clock off
Setting this bit allows the external CLKOUT pin of the
SJA1000 to be disabled. A write access is possible only in
reset mode. If this bit is set, CLKOUT is LOW during sleep
mode, otherwise it is HIGH.
6.5.4.3 RXINTEN
This bit allows the TX1 output to be used as a dedicated
receive interrupt output. When a received message has
passed the acceptance filter successfully, a receive
interrupt pulse with the length of one bit time is always
output at the TX1 pin (during the last bit of end of frame).
The transmit output stage should operate in normal output
mode. The polarity and output drive are programmable via
the output control register (see also Section 6.5.3). A write
access is only possible in reset mode.
6.5.4.4 CBP
Setting of CDR.6 allows to bypass the CAN input
comparator and is only possible in reset mode. This is
useful in the event that the SJA1000 is connected to an
external transceiver circuit. The internal delay of the
SJA1000 is reduced, which will result in a longer maximum
possible bus length. If CBP is set, only RX0 is active. The
unused RX1 input should be connected to a defined level
(e.g. V
SS
).
6.5.4.5 CAN mode
CDR.7 defines the CAN mode. If CDR.7 is at logic 0 the
CAN controller operates in BasicCAN mode. If set to
logic 1 the CAN controller operates in PeliCAN mode.
Write access is only possible in reset mode.
2000 Jan 04 57
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all voltages referenced to V
SS
.
Notes
1. I
OT
is allowed in case of a bus failure condition because then the TX outputs are switched off automatically after a
short time (bus-off state). During normal operation I
OT
is a peak current, permitted for t < 100 ms. The average output
current must not exceed 10 mA for each TX output.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on
device power consumption.
3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor.
4. Machine model: equivalent to discharging a 200 pF capacitor through a 25 plus 2.5 µH circuit.
8 THERMAL CHARACTERISTICS
9 DC CHARACTERISTICS
V
DD
= 5 V (±10%); V
SS
=0V; T
amb
= 40 to +125 °C; all voltages referenced to V
SS
; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
supply voltage 0.5 +6.5 V
I
I
, I
O
input/output current on all pins except
TX0 and TX1
−±4mA
I
OT(sink)
sink current of TX0 and TX1 together note 1 30 mA
I
OT(source)
source current of TX0 and TX1
together
note 1 −−20 mA
T
amb
operating ambient temperature 40 +125 °C
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation note 2 1.0 W
V
esd
electrostatic discharge on all pins note 3 1500 +1500 V
note 4 200 +200 V
SYMBOL PARAMETER CONDITION VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 67 K/W
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Supplies
V
DD
supply voltage 4.5 5.5 V
I
DD
operating supply current f
osc
= 24 MHz; note 1 15 mA
I
sm
sleep mode supply current oscillator inactive; note 2 40 µA

SJA1000T/N1,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC STAND-ALONE CAN CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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