AD9042ASTZ Datasheet AD9042ASTZ | P16-P18

AD9042

Rev. B | Page 15 of 24

OUTPUT LOADING

When calculating the proper termination resistor, note that the

external load resistor is in parallel with the AD9042 analog

input resistance, 250 Ω. The external resistor value can be

calculated from the following equation:

Care must be taken when designing the data receivers for the

AD9042. It is recommended that the digital outputs drive a

series resistor of 499 Ω followed by a CMOS gate such as the

74AC574. To minimize capacitive loading, there should be only

one gate on each output pin. The digital outputs of the AD9042

have a unique constant slew rate output stage. The output slew

rate is about 1 V/ns independent of output loading. A typical

CMOS gate combined with PCB trace and through hole has a

load of approximately 10 pF. Therefore, as each bit switches, 10 mA

of dynamic current per bit flows in or out of the device. A full-

scale transition can cause up to 120 mA (12 bits × 10 mA/bit) of

current to flow through the digital output stage. The series

resistor minimizes the output currents that can flow in the

output stage. These switching currents are confined between

ground and the DV

pin. Standard TTL gates should be

avoided because they can appreciably add to the dynamic

switching currents of the AD9042.

250

−

where

Z is desired impedance.

A dc-coupled input configuration (shown in Figure 35) is

limited by the drive amplifier performance. The on-chip

reference of the AD9042 is buffered using the OP279 dual, rail-

to-rail operational amplifier. The resulting voltage is combined

with the analog source using an AD9631. Pending improvements

in drive amplifiers, this dc-coupled approach is limited to ~75 dB

to 80 dB of dynamic performance depending on which drive

amplifier is used. The AD9631 and OP279 run off ±5 V.

SIGNAL

SOURCE

0pF

50pF

AD9631

50Ω

0.1µF

AD9042

AIN

OFFSET

REF

200Ω

114Ω

49.9Ω

OP279

(1/2)

OP279

(1/2)

571Ω

1kΩ

79Ω

21Ω

00554-041

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⎠

⎞

⎜

⎝

⎛

LAYOUT INFORMATION

The pinout of the AD9042 facilitates ease of use and the

implementation of high frequency/high resolution design

practices. All of the digital outputs are on one side of the

package, and all of the inputs are on the other sides of the

package. It is highly recommended that high quality ceramic

chip capacitors be used to decouple each supply pin to ground

directly at the device. Depending on the configuration used for

the encode and analog inputs, one or more capacitors are

required on those input pins. The capacitors used on the

ENCODE

and V

REF

pins must be low inductance chip capacitors

as noted previously.

Figure 35. DC-Coupled Analog Input Circuit

POWER SUPPLIES

Care should be taken when selecting a power source. Linear

supplies are strongly recommended because switching supplies

tend to have radiated components that may be received by the

AD9042. Each of the power supply pins should be decoupled as

close to the package as possible using 0.1 μF chip capacitors.

The AD9042 has separate digital and analog 5 V pins. The AV

pins are the analog supply pins, and the DV

pins are the

digital supply pins. Although analog and digital supplies may

be tied together, best performance is achieved when the supplies

are separate. This is because the fast digital output swings can

couple switching noise back into the analog supplies. Note that

must be held within 5% of 5 V.

Although a multilayer board is recommended, it is not required

to achieve good results. Care should be taken when placing the

digital output runs. Because the digital outputs have such a high

slew rate, the capacitive loading on the digital outputs should be

minimized. Circuit traces for the digital outputs should be kept

short and connected directly to the receiving gate (broken only

by the insertion of the series resistor). Logic fanout for each bit

should be one CMOS gate.

AD9042

Rev. B | Page 16 of 24

DIGITAL WIDEBAND RECEIVERS

INTRODUCTION

Several key technologies are now being introduced that may

forever alter the vision of radio. Figure 36 shows the typical dual

conversion superheterodyne receiver. The signal picked up by

the antenna is mixed down to an intermediate frequency (IF)

using a mixer with a variable local oscillator (LO); the variable

LO is used to tune in the desired signal. This first IF is mixed

down to a second IF using another mixer stage and a fixed LO.

Demodulation takes place at the second or third IF using either

analog or digital techniques.

ADCs

VARIABLE

FIXED

NARROW-BAND

FILTER

NARROW-BAND

FILTER

LNA

900MHz

SHARED ONE RECEIVER PER CHANNEL

00554-054

Figure 36. Narrow-Band Digital Receiver Architecture

If demodulation takes place in the analog domain, then traditional

discriminators, envelope detectors, phase-locked loops, or other

synchronous detectors are generally used to strip the modulation

from the selected carrier.

However, as general-purpose DSP chips such as the ADSP-2181

become more popular, they can be used in many baseband

sampled application such as the one shown in Figure 36. As

shown in the figure, prior to ADC conversion, the signal must be

mixed down and filtered, and the I and Q components must be

separated. These functions are realized through DSP techniques;

however, several key technology breakthroughs are required:

high dynamic range ADCs, such as the AD9042, new DSPs

(highly programmable with fast onboard memory), digital

tuner and filter (with programmable frequency and BW), and

wideband mixers (high dynamic range with >12.5 MHz BW).

WIDEBAND

ADC

FIXED

WIDEBAND

MIXER

WIDEBAND

FILTER

LNA

900MHz

SHARED

"n" CHANNELS

TO DSP

12.5MHz

(416 CHANNELS)

CHANNEL SELECTION

00554-055

Figure 37. Wideband Digital Receiver Architecture

Figure 37 shows such a wideband system. This design shows

that the front-end variable local oscillator has been replaced

with a fixed oscillator (for single-band radios), and the back end

has been replaced with a wide dynamic range ADC, digital

tuner, and DSP. This technique offers many benefits.

First, many passive discrete components that formed the tuning

and filtering functions have been eliminated. These passive

components often require adjusting and special handling

during assembly and final system alignment. Digital

components require no such adjustments; tuner and filter

characteristics are always exactly the same. Moreover, the

tuning and filtering characteristics can be changed through

software. Because software is used for demodulation, different

routines may be used to demodulate different standards such as

AM, FM, GMSK, or any other desired standard. In addition, as

new standards arise or new software revisions are generated,

they may be field installed with standard software update

channels. A radio that performs demodulation in software as

opposed to hardware is often referred to as a soft radio because

it can be changed or modified simply through code revision.

System Description

In the wideband digital radio (see Figure 37), the first down-

conversion functions in much the same way as a block converter

does. An entire band is shifted in frequency to the desired

intermediate frequency. In the case of cellular base station

receivers, 5 MHz to 20 MHz of bandwidth are downconverted

simultaneously to an IF frequency suitable for digitizing with a

wideband ADC. Once digitized, the broadband digital data

stream contains all of the in-band signals. The remainder of the

radio is constructed digitally using special-purpose and general-

purpose programmable DSP to perform filtering, demodulation,

and signal conditioning, not unlike the analog counterparts.

In the narrow-band receiver (see Figure 36), the signal to be

received must be tuned. This is accomplished by using a

variable local oscillator at the first mix-down stage. The first IF

then uses a narrow-band filter to reject out-of-band signals and

condition the selected carrier for signal demodulation.

In the digital wideband receiver (see Figure 37), the variable

local oscillator has been replaced with a fixed oscillator, so

tuning must be accomplished in another manner. Tuning is

performed digitally using a digital downconversion and a filter

chip frequently called a channelizer. The term, channelizer, is

used because the purpose of these chips is to select one channel

out of the many within the broadband of spectrum actually

present in the digital data stream of the ADC.

DECIMATION

FILTER

LOW-PASS

FILTER

DIGITAL

TUNER

COS

SIN

DECIMATION

FILTER

LOW-PASS

FILTER

DATA

00554-056

Figure 38. Digital Channelizer

AD9042

Rev. B | Page 17 of 24

Figure 38 shows the block diagram of a typical channelizer.

Channelizers consist of a complex NCO (numerically controlled

oscillator), dual multiplier (mixer), and matched digital filters.

These are the same functions that would be required in an

analog receiver but implemented in digital form. The digital

output from the channelizer is the desired carrier, frequently in

I and Q format; all other signals are filtered and removed based

on the filtering characteristics desired. Because the channelizer

output consists of one selected RF channel, one tuner chip is

required for each frequency received, although only one

wideband RF receiver is needed for the entire band. Data from

the channelizer can then be processed using a digital signal

processor such as the ADSP-2181 or the SHARC ADSP-21062

processor. This data may then be processed through software to

demodulate the information from the carrier.

Figure 39 shows a typical wideband receiver subsystem based

around the AD9042. This strip consists of a wideband IF filter,

amplifier, ADC, latches, channelizer, and interface to a digital

signal processor. This design shows a typical clocking scheme

used in many receiver designs. All timing within the system is

referenced back to a single clock. Although this is not necessary,

it facilitates PLL design, ease of manufacturing, system test, and

calibration. Keeping in mind that the overall performance goal

is to maintain the best possible dynamic range, many choices

must be considered.

One of the biggest challenges is selecting the amplifier used to

drive the AD9042. Because this is a communications application,

the key specification for this amplifier is spurious-free dynamic

range (SFDR). An amplifier should be selected that can provide

SFDR performance better than 80 dB into 250 Ω. One such

amplifier is the AD9631. These low spurious levels are necessary

because harmonics due to the drive amplifier and ADC can

distort the desired signals of interest.

Two other key considerations for the digital wideband receiver

are converter sample rate and IF frequency range. Because

performance of the AD9042 converter is nearly independent

of both sample rate and analog input frequency (see Figure 6,

Figure 7, and Figure 10), the designer has greater flexibility in the

selection of these parameters. Also, because the AD9042 is a

bipolar device, power dissipation is not a function of sample

rate. Thus, there is no penalty paid in power by operating at

faster sample rates. By carefully selecting input frequency range

and sample rate, the drive amplifier and ADC harmonics can

actually be placed out-of-band. Thus, other components such as

filters and IF amplifiers may actually end up being the limiting

factor on dynamic range.

For example, if the system has second and third harmonics that

are unacceptably high, the careful selection of the encode rate

and signal bandwidth can place these second and third harmonics

out-of-band. For the case of an encode rate equal to 40.96 MSPS

and a signal bandwidth of 5.12 MHz, placing the fundamental

at 5.12 MHz places the second and third harmonics out-of-

band as shown in Table 7.

Table 7. Example Frequency Plan

Parameter Value

Encode Rate 40.96 MSPS

Fundamental 5.12 MHz to 10.24 MHz

Second Harmonic 10.24 MHz to 20.48 MHz

Third Harmonic 15.36 MHz to 10.24 MHz

Another option is found through band-pass sampling. If the

analog input signal range is from dc to FS/2, then the amplifier

and filter combination must perform to the specification required.

However, if the signal is placed in the third Nyquist zone (FS to

3 FS/2), the amplifier is no longer required to meet the harmonic

performance required by the system specifications because all

harmonics fall outside the pass-band filter. For example, the

pass-band filter ranges from f

to 3 FS/2. The second harmonic

would span from 2 FS to 3 FS, well outside the range of the

pass-band filter. The burden then is placed on the filter design,

provided that the ADC meets the basic specifications at the

frequency of interest. In many applications, this is a worthwhile

trade-off because many complex filters can easily be realized

using SAW and LCR techniques alike at these relatively high IF

frequencies. Although the harmonic performance of the drive

amplifier is relaxed by this technique, intermodulation

performance cannot be sacrificed because intermods must be

assumed to fall in-band for both amplifiers and converters.

PRESELECT

FILTER

LNA

5MHz TO 15MHz

PASS BAND

CMOS

BUFFER

D11

5V (D)5V (A)

AD9042

AIN

ENCODE

M/N PLL

SYNTHESIZER

DRIVE

REF

864MHz

REFERENCE

CLOCK

40.96MHz

CHANNELIZER

I AND Q

DATA

CLK

ADSP-2181

NETWORK

CONTROLLER

INTERFACE

499Ω

00554-057

Figure 39. Simplified 5 MHz Wideband “A” Carrier Receiver

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD9042ASTZ

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 12-Bit 41MSPS Monolithic

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