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Document History Page
Document Title: SL28504 Clock Generator for Intel
Eaglelake Chipset
REV. ECR# Issue Date
Orig. of
Change Description of Change
1.0 10/5/07 BSHEN Initial Release
1.1 10/19/07 BSHEN Add SRC1 to pin 17/18. and tri-level trigger at 24.576M
1.2 01/21/08 BSHEN 1. Change Revision ID Byte7[7:4] to be 0001
2. Updated block diagram
3. Change Byte10[6:2] and Byte11[4] to be reserved
1.3 05/26/09 BSHEN 1. Update TSSOP64 package dimension to compliant to SLI-POD spec
1.4 06/24/09 BSHEN 1. Correct the pin out with CLK request pin
2. Correct the CLK request register
3. Remove QFN package,
AA 1576 04/28/10 BSHEN 1. Updated Industrial ordering information
2. Correct VDD_IO pin description
3. Updated document format for ISO compliance.
