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SL28504BZI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
SL28504
........................DOC #: SP-AP-0052 (Rev. AA) Page 7 of 31
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave–8 bits
.... Data Byte N–8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave–8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave–8 bits
.... NOT Acknowledge
.... Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address–7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave–8 bits
38 NOT Acknowledge
39 Stop
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
SL28504
........................DOC #: SP-AP-0052 (Rev. AA) Page 8 of 31
Control Registers
Byte 0: Control Register 0
Bit @Pup Name Description
7 HW FS_C CPU Frequency Select Bit, set by HW
6 HW FS_B CPU Frequency Select Bit, set by HW
5 HW FS_A CPU Frequency Select Bit, set by HW
4 0 iAMT_EN Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
3 0 Reserved Reserved
2 0 Reserved Reserved
1 0 SATA_SEL Select source of SATA clock
0 = PLL3, 1= PLL4
0 1 PD_Restore Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
Byte 1: Control Register 1
Bit @Pup Name Description
7 0 SRC0_SEL Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
6 0 PLL1_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
5 0 PLL3_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 1 Reserved Reserved
0 1 PCI_SEL Select source of PCI clocks
0=PLL1, 1=PLL3
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 REF0_OE Output enable for REF0
0 = Output Disabled, 1 = Output Enabled
6 1 USB48_OE Output enable for USB48
0 = Output Disabled, 1 = Output Enabled
5 1 PCIF0_OE Output enable for PCIF5
0 = Output Disabled, 1 = Output Enabled
4 1 PCI4_OE Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
3 1 PCI3_OE Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
2 1 PCI2_OE Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
1 1 PCI1_OE Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
0 1 PCI0_OE Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
SL28504
........................DOC #: SP-AP-0052 (Rev. AA) Page 9 of 31
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 SRC11_OE Output enable for SRC11
0 = Output Disabled, 1 = Output Enabled
6 1 SRC10_OE Output enable for SRC10
0 = Output Disabled, 1 = Output Enabled
5 1 SRC9_OE Output enable for SRC9
0 = Output Disabled, 1 = Output Enabled
4 1 SRC8/CPU2_ITP_OE Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
3 1 SRC7_OE Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
2 1 SRC6_OE Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1 1 RESERVED RESERVED
0 1 SRC4_OE Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit @Pup Name Description
7 1 SRC3_OE Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6 1 SRC2/SATA_OE Output enable for SRC2/SATA
0 = Output Disabled, 1 = Output Enabled
5 1 SRC1_OE Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
4 1 SRC0/DOT96_OE Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
3 1 CPU1_OE Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2 1 CPU0_OE Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1 1 PLL1_SS_EN Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0 1 PLL3_SS_EN Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 CR#_A_EN Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
6 0 CR#_A_SEL Set CR#_A SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
5 0 CR#_B_EN Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
4 0 CR#_B_SEL Set CR#_B SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
3 0 CR#_C_EN Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
2 0 CR#_C_SEL Set CR#_C SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

SL28504BZI

Mfr. #:
Buy SL28504BZI
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Syst Clock Intel Eaglake
Lifecycle:
New from this manufacturer.
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