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SL28504BZI

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SL28504
........................DOC #: SP-AP-0052 (Rev. AA) Page 4 of 31
34 SRC10 O, DIF 100 MHz Differential serial reference clocks.
35 SRC#10 O, DIF 100 MHz Differential serial reference clocks.
36 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs.
37 CPU_STOP#/SRC5# I/O,
Dif
3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference
clocks. The option is selected by SRC5_EN
38 PCI_STOP#/SRC5 I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs./ 100 MHz Differential serial
reference clocks.The option is selected by SRC5_EN
39 VDD_SRC PWR 3.3V Power supply for SRC PLL.
40 SRC6# O, DIF 100 MHz Differential serial reference clocks.
41 SRC6 O, DIF 100 MHz Differential serial reference clocks.
42 VSS_SRC GND Ground for outputs.
43 SRC7# O, DIF 100 MHz Differential serial reference clocks
44 SRC7 O, DIF 00 MHz Differential serial reference clocks
45 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs.
46 SRC8#/CPUC2_ITP# O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
47 SRC8/CPUT2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
48 SEL_24.576M I, PD Select 25M1_24.576M output and SRC1
0 = 25M1, M= SRC1, 1 = 24.576M
49 VDD_CPU_IO PWR 3.3V-1.05V power supply for CPU outputs.
50 CPU1# O, DIF Differential CPU clock outputs.
Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
51 CPU1 O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
52 VSS_CPU GND Ground for outputs.
53 CPU0# O, DIF Differential CPU clock outputs.
54 CPU0 O, DIF Differential CPU clock outputs.
55 VDD_CPU PWR 3.3V Power supply for CPU PLL.
56 CK_PWRGD/PWRDWN# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
57 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58 VSS_REF GND Ground for outputs.
59 XTAL_OUT O, SE 14.318 MHz Crystal output.
60 XTAL_IN I 14.318 MHz Crystal input.
61 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to V
IHFS_C
when CK_PWRGD is asserted HIGH. Refer to DC
Electrical Specifications table for V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifications.
64-TSSOP Pin Definitions
Pin No. Name Type Description
SL28504
........................DOC #: SP-AP-0052 (Rev. AA) Page 5 of 31
63 SMB_DATA I/O SMBus compatible SDATA.
64 SMB_CLK I SMBus compatible SCLOCK.
64-TSSOP Pin Definitions
Pin No. Name Type Description
SL28504
........................DOC #: SP-AP-0052 (Rev. AA) Page 6 of 31
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
Frequency Select Pin (FSA, FSB and FSC)
FSC FSB FSA CPU SRC PCIF/PCI REF DOT96 USB
000266 MHz
100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz
001133 MHz
010200 MHz
011166 MHz
100333 MHz
101100 MHz
110400 MHz
1 1 1 Reserved Reserved
Table 1. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Byte Count–8 bits
(Skip this step if I
2
C_EN bit set)
20 Repeat start
28 Acknowledge from slave 27:21 Slave address–7 bits
36:29 Data byte 1–8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2–8 bits 37:30 Byte Count from slave–8 bits
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SL28504BZI

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Buy SL28504BZI
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Syst Clock Intel Eaglake
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