Operation M41T315Y, M41T315V, M41T315W
14/30
Figure 8. Comparison register definition
Note: Pattern recognition in “hex” is C5, 3A, A3, 5C, C5, 3A, A3, and 5C. The odds of this pattern
being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 10
19
.
This pattern is sent to the clock LSB to MSB.
2.2 Data retention
Most low power SRAMs on the market today can be used with the M41T315Y/V/W. There
are, however some criteria which should be used in making the final choice of an SRAM to
use. The SRAM must be designed in a way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the M41T315Y/V/W and SRAMs to be Don’t Care
once V
CCI
falls below V
PFD
(min). The SRAM should also guarantee data retention down to
V
CC
= 2.0 volts. The chip enable access time must be sufficient to meet the system needs
with the chip enable output propagation delays included. If the SRAM includes a second
chip enable pin (E2), this pin should be tied to V
OUT
.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 volts. Manufacturers generally specify a typical
condition for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
7
65 432
1
0
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
Hex
Value
0
10
0
0
1
1
1
1
01
1
1
0
0
0
1
10
0
1
0
0
1
0
01
1
0
1
1
0
0
10
0
0
1
1
1
1
01
1
1
0
0
0
1
10
0
1
0
0
1
0
01
1
0
1
1
0
C5
3A
A3
5C
C5
3A
A3
5C
AI04262
