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ADA4859-3ACPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADA4859-3 Data Sheet
Rev. A | Page 12 of 16
THEORY OF OPERATION
OVERVIEW
The ADA4859-3 is a fixed gain of two, current feedback amplifier
designed for exceptional performance as a triple video amplifier. Its
specifications make it especially suitable for SD and HD video
applications. The ADA4859-3 provides HD video output on a
single supply as low as 3.0 V while only consuming 13 mA per
amplifier. It also features a power-down pin (PD) that reduces
the quiescent current to 4 mA when activated.
The ADA4859-3 can be used in applications that require both
ac- and dc-coupled inputs and outputs. The output stage on the
ADA4859-3 is capable of driving 2 V p-p video signals into two
doubly terminated video loads (150 Ω each) on a single 5 V supply.
The input range of the ADA4859-3 includes ground, whereas
the output range is limited by the output headroom set by the
voltage drop across two diodes from each rail, which occurs
1.2 V from the positive and negative supply rails.
CHARGE PUMP OPERATION
The on-board charge pump creates a negative supply for the
amplifier. It provides different negative voltages depending on
the power supply voltage. For a +5 V supply, the negative supply
generated is equal to −3 V with 150 mA of output supply current,
and for a +3.3 V supply, the negative supply is equal to −2 V
with 45 mA of output supply current.
Figure 30 shows the charging cycle when the supply voltage, +V
S
,
charges C1 through Φ
1
to ground. During this cycle, C1 quickly
charges to reach the +V
S
voltage. The discharge cycle then begins
with switching Φ
1
off and switching Φ
2
on, as shown in Figure 31.
When C1 = C2, the charge in C1 is divided between the two
capacitors and slowly increases the voltage in C2 until it reaches a
predetermined voltage (−3 V for the +5 V supply and −2 V for
the +3.3 V supply). The typical charge pump charging and
discharging frequency is 550 kHz with a 150 Ω load and no input
signal. This frequency changes with the load current, and it can
get much slower if the amplifier is powered down and no external
current is used.
07715-137
+V
S
CPO
C2
C1
Φ
1
Φ
1
a
b
Figure 30. Charging Cycle
07715-138
+V
S
CPO
C2
C1
Φ
2
Φ
2
a
b
Figure 31. Discharging Cycle
The ADA4859-3 specifications make it especially suitable for SD
and HD video applications. It also allows dc-coupled video signal
with its black level set to 0 V and its sync tip down to −300 mV
for YPbPr video.
The charge pump is always on, even when the power-down pin
(PD) is enabled and the amplifier is off. However, it would be in
an idle state if the negative current were not used. Each amplifier
needs −6.3 mA of current, which totals −19 mA for all three
amplifiers. This means additional negative current may be available
by the charge pump for external use. Pin 4 (CPO) is the charge
pump output, which provides access to the negative supply
generated by the charge pump. Placing a 1 µF charge capacitor at
the CPO pin is essential to hold the charge and regulate the ripple.
If the negative supply is used to power another device in the
system, it is only possible for the 5 V supply operation. In the
3.3 V supply operation, the charge pump output current is very
limited. The capacitor at the CPO pin, which regulates the ripple
of the negative voltage, can be used as a coupling capacitor for the
external device. However, the charge pump current should be
limited to a maximum of 50 mA for external use. When powering
down the ADA4859-3, the charge pump is not affected and its
output voltage and current remain available for external use.
Data Sheet ADA4859-3
Rev. A | Page 13 of 16
APPLICATIONS INFORMATION
USING THE ADA4859-3 IN GAINS EQUAL TO +1, −1
The ADA4859-3 was designed to offer outstanding video
performance, simplify applications, and minimize board area.
The ADA4859-3 is a triple amplifier with on-chip feedback
and gain set resistors. The gain is fixed internally at G = +2. The
inclusion of the on-chip resistors not only simplifies the design
of the application but also eliminates six surface-mount resistors,
saving valuable board space and lowering assembly costs.
Although the ADA4859-3 has a fixed gain of G = +2, it can be
used in other gain configurations, such as G = −1 and G = +1.
Unity-Gain Operation
Option 1
There are two options for obtaining unity gain (G = +1). The
first is shown in Figure 32. In this configuration, the −IN input
pin is tied to the output. (Feedback is provided through the two
internal 550 Ω resistors in parallel), and the input is applied to
the noninverting input. The noise gain for this configuration is 1.
0.1µF
10µF
V
IN
R
T
V
OUT
+V
S
GAIN OF +1
07715-130
Figure 32. Unity Gain of Option 1
Option 2
Another option exists for running the ADA4859-3 as a unity-
gain amplifier. In this configuration, the noise gain is +2, see
Figure 33. The frequency response and transient response for
this configuration closely match the gain of +2 plots because the
noise gains are equal. This method does have twice the noise
gain of Option 1; however, in applications that do not require low
noise, Option 2 offers less peaking and ringing. By tying the inputs
together, the net gain of the amplifier becomes +1. Equation 1
shows the transfer characteristic for the schematic shown in
Figure 33.
+
+
−
=
G
G
F
IN
G
F
IN
OUT
R
R
R
V
R
R
VV
(1)
which simplifies to V
OUT
= V
IN
.
0.1µF
V
IN
R
T
V
OUT
+V
S
GAIN OF +1
07715-131
10µF
R
F
R
G
Figure 33. Unity Gain of Option 2
Inverting Unity-Gain Operation
In this configuration, the noninverting input is tied to ground
and the input signal is applied to the inverting input. The noise
gain for this configuration is +2, see Figure 34.
0.01µF
V
IN
R
T
V
OUT
+V
S
GAIN OF –1
07715-132
10µF
Figure 34. Inverting Configuration (G = −1)
Figure 35 shows the small signal frequency response for both
gain of +1 (Option 1 and Option 2) and gain of −1 configurations.
It is clear that the G = +1 Option 2 has better flatness and no
peaking compared to Option 1.
3
–9
–6
–3
0
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
G = +1,
OPTION 1
G = +1,
OPTION 2
G = –1
07715-031
V
S
= 5V
V
OUT
= 2V p-p
R
L
= 100Ω
Figure 35. Large Signal, G = +1 and G = −1
ADA4859-3 Data Sheet
Rev. A | Page 14 of 16
VIDEO LINE DRIVER
The ADA4859-3 was designed to excel in video driver applications.
Figure 36 shows a typical schematic for a video driver operating
on bipolar supplies.
07715-134
1
2
3
4
11
12
CHARGE
PUMP
10
9
5 6 7 8
16 15 14 13
1µF
+
10µF 0.1µF
+V
S
1µF
V
IN
(B)
75Ω
75Ω
V
OUT
(B)
75Ω
V
OUT
(G)
75Ω
V
OUT
(R)
75Ω
V
IN
(G)
75Ω
V
IN
(R)
PD
Figure 36. Video Driver Schematic
In applications that require multiple video loads be driven
simultaneously, the ADA4859-3 can deliver. Figure 37 shows
the ADA4859-3 configured with two video loads, and Figure 38
shows the large signal performance for multiple video loads.
07715-135
75Ω
CABLE
75Ω
CABLE
75Ω
75Ω
75Ω
75Ω
V
OUT
2
V
OUT
1
+V
S
0.1µF
10µF
V
IN
75Ω
CABLE
75Ω
+
–
Figure 37. Video Driver Schematic for Two Video Loads
6.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
R
L
= 150Ω
R
L
= 75Ω
07715-034
Figure 38. Large Signal Frequency Response for Various Loads
POWER-DOWN
The ADA4859-3 is equipped with a PD (power-down) pin for
all three amplifiers. This allows the user the ability to reduce the
quiescent supply current when an amplifier is not active. The
power-down threshold levels are derived from ground level.
The amplifiers are powered down when the voltage applied to
the PD pin is greater than a certain voltage from ground. In a 5 V
supply application, the voltage is greater than 2 V, and in a 3.3 V
supply application, the voltage is greater than 1.5 V. The amplifier
is enabled whenever the PD pin is connected to ground. If the
PD pin is not used, it is best to connect it to ground. Note that
the power-down feature does not control the charge pump output
voltage and current.
Table 5. Power-Down Voltage Control
PD Pin 5 V 3.3 V
Not Active <1.5 V <1 V
Active >2 V >1.5 V
LAYOUT CONSIDERATIONS
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board to
provide a low impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
reduces stray capacitance. Locate termination resistors and loads as
close as possible to their respective inputs and outputs. Keep
input and output traces as far apart as possible to minimize
coupling (crosstalk) through the board. Adherence to microstrip or
stripline design techniques for long signal traces (greater than
about 1 inch) is recommended.
POWER SUPPLY BYPASSING
Careful attention must be paid to bypassing the power supply pins
of the ADA4859-3. Use high quality capacitors with low equivalent
series resistance (ESR), such as multilayer ceramic capacitors
(MLCCs), to minimize supply voltage ripple and power dissipation.
A large, usually tantalum, 10 µF to 47 µF capacitor located in
proximity to the ADA4859-3 is required to provide good
decoupling for lower frequency signals. In addition, locate 0.1 µF
MLCC decoupling capacitors as close to each of the power supply
pins as is physically possible, no more than 1/8-inch away. The
ground returns should terminate immediately into the ground
plane. Locating the bypass capacitor return close to the load
return minimizes ground loops and improves performance.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADA4859-3ACPZ-R7

Mfr. #:
Buy ADA4859-3ACPZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Video Amplifiers SGL-Supply Hi Spd w/ Charge Pump
Lifecycle:
New from this manufacturer.
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