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9ZML1232BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DATASHEET
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
9ZML1232
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 1
9ZML1232 REV E 112015
General Description
The 9ZML1232 is a 2-input/12-output differential mux for
use in servers. It meets the demanding DB1200ZL
performance specifications and utilizes Low-Power
HCSL-compatible outputs to reduce power consumption
and termination components. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI
applications.
Recommended Application
Clock Mux for Romley, Grantley and Purley Servers
Output Features
• 12 - Low-Power (LP) HCSL Output Pairs
Features/Benefits
• Fixed feedback path; 0ps input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can
share same SMBus segment
• Separate VDDIO for outputs; allows maximum power
savings
• PLL or bypass mode; PLL can dejitter incoming clock
• Hardware or Software-selectable PLL BW; minimizes
jitter peaking in downstream PLL's
• Spread spectrum compatible; tracks spreading input
clock for EMI reduction
• SMBus Interface; unused outputs can be disabled
• Differential outputs are Low/Low in power down;
maximum power savings
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <65 ps
• Input-to-output delay: Fixed at 0 ps
• Input-to-output delay variation <50ps
• Phase jitter: PCIe Gen3 <1ps rms
• Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
Block Diagram
Logic
yy
DIF(11:0)
HIBW_BYPM_LOBW#
SMBDAT
SMBCLK
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
Z-PLL
(SS Compatible)
FBOUT_NC
DIF_INA
DIF_INA#
OE(11:0)#
SEL_A_B#
DIF_INB
DIF_INB#
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 2
9ZML1232 REV E 112015
Pin Configuration
Power Management Table
PLL Operating Mode Table
Power Connections
Tri-Level Input Thresholds
9ZML1232 SMBus Addressing
^OE11#
^OE10#
GND
VDDIO
DIF_11#
DIF_11
DIF_10#
DIF_10
VDD
GND
DIF_9#
DIF_9
DIF_8#
DIF_8
GND
VDDIO
^OE9#
^OE8#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1 54
^OE7#
GNDA 2 53
^OE6#
^SEL_A_B# 3 52
VDDIO
^
vHIBW_BYPM_LOBW#
4 51
GND
CKPWRGD_PD# 5 50
DIF_7#
DIF_INB 6 49
DIF_7
DIF_INB# 7 48
DIF_6#
GND 8 47
DIF_6
VDDR 9 46
GND
DIF_INA 10 45
VDD
DIF_INA# 11 44
DIF_5#
vSMB_A0_tri 12 43
DIF_5
SMBDAT 13 42
DIF_4#
SMBCLK 14 41
DIF_4
vSMB_A1_tri 15 40
VDDIO
GND 16 39
GND
FBOUT_NC# 17 38
^OE5#
FBOUT_NC 18 37
^OE4#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
^OE0#
^OE1#
VDDIO
GND
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
VDDIO
GND
^OE2#
^OE3#
9ZML1232
^ prefix indicates internal 120Kohm Pull Up
v prefix indicates internal 120Kohm Pull down
10mm x 10mm 72-MLF, 0.5mm pin pitch
Control Bits
CKPWRGD_PD#
DIF_IN/
DIF_IN#
SMBus
EN bit
DIFx/
DIFx#
FBOUT_NC/
FB_OUT_NC#
0 X X Low/Low Low/Low
OFF
0 Low/Low Running ON
1 Running Running
ON
Inputs
PLL State
1 Running
Outputs
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW) 00
Mid (Bypass) 01
High (PLL High BW) 11
NOTE: PLL is off in Bypass mode
VDD VDDIO GND
12
Analo
g
PL
L
9 8 Analog Input
28, 45, 64
21, 33, 40,
52, 57, 69
16, 22, 27, 34,
39, 46, 51, 58,
63, 70
DIF clocks
Pin Number
Description
Level Voltage
Low
<0.8V
Mid 1.2<Vin<1.8V
High Vin > 2.2V
SMBus Address
(
Rd/Wrt bit = 0
)
D8
DA
C2
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 3
9ZML1232 REV E 112015
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GNDA PWR Ground pin for the PLL core.
3 ^SEL_A_B# IN
Input to select differential input clock A or differential input clock B. This input has
an internal pull-up resistor.
0 = Input B selected, 1 = Input A selected.
4 ^vHIBW_BYPM_LOBW#
LATCHE
D IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
5 CKPWRGD_PD# IN
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
6 DIF_INB IN 0.7 V HCSL-Compatible Differential True input
7 DIF_INB# IN 0.7 V HCSL-Compatible Differential Complement Input
8 GND PWR Ground pin.
9 VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be treated as
an analog power rail and filtered appropriately.
10 DIF_INA IN 0.7 V HCSL-Compatible Differential True input
11 DIF_INA# IN 0.7 V HCSL-Compatible Differential Complement Input
12 vSMB_A0_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the
SMB_A1 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull
down resistor.
13 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
14 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
15 vSMB_A1_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the
SMB_A0 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull
down resistor.
16 GND PWR Ground pin.
17 FBOUT_NC# OUT
Complementary half of differential feedback output. This pin should NOT be
connected to anything outside the chip. It exists to provide delay path matching to
get 0 propagation delay.
18 FBOUT_NC OUT
True half of differential feedback output. This pin should NOT be connected to
anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
19 ^OE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
20 ^OE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
21 VDDIO PWR Power supply for differential outputs
22 GND PWR Ground pin.
23 DIF_0 OUT 0.7V differential true clock output
24 DIF_0# OUT 0.7V differential Complementary clock output
25 DIF_1 OUT 0.7V differential true clock output
26 DIF_1# OUT 0.7V differential Complementary clock output
27 GND PWR Ground pin.
28 VDD PWR Power supply, nominal 3.3V
29 DIF_2 OUT 0.7V differential true clock output
30 DIF_2# OUT 0.7V differential Complementary clock output
31 DIF_3 OUT 0.7V differential true clock output
32 DIF_3# OUT 0.7V differential Complementary clock output
33 VDDIO PWR Power supply for differential outputs
34 GND PWR Ground pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9ZML1232BKLF

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Buy 9ZML1232BKLF
Manufacturer:
IDT
Description:
Clock Buffer Buffer
Lifecycle:
New from this manufacturer.
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