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9ZML1232BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 4
9ZML1232 REV E 112015
Pin Descriptions (cont.)
PIN # PIN NAME PIN TYPE DESCRIPTION
35 ^OE2# IN
Active low input for enabling DIF pair 2. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
36 ^OE3# IN
Active low input for enabling DIF pair 3. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
37 ^OE4# IN
Active low input for enabling DIF pair 4. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
38 ^OE5# IN
Active low input for enabling DIF pair 5. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
39 GND PWR Ground pin.
40 VDDIO PWR Power supply for differential outputs
41 DIF_4 OUT 0.7V differential true clock output
42 DIF_4# OUT 0.7V differential Complementary clock output
43 DIF_5 OUT 0.7V differential true clock output
44 DIF_5# OUT 0.7V differential Complementary clock output
45 VDD PWR Power supply, nominal 3.3V
46 GND PWR Ground pin.
47 DIF_6 OUT 0.7V differential true clock output
48 DIF_6# OUT 0.7V differential Complementary clock output
49 DIF_7 OUT 0.7V differential true clock output
50 DIF_7# OUT 0.7V differential Complementary clock output
51 GND PWR Ground pin.
52 VDDIO PWR Power supply for differential outputs
53 ^OE6# IN
Active low input for enabling DIF pair 6. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
54 ^OE7# IN
Active low input for enabling DIF pair 7. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
55 ^OE8# IN
Active low input for enabling DIF pair 8. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
56 ^OE9# IN
Active low input for enabling DIF pair 9. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
57 VDDIO PWR Power supply for differential outputs
58 GND PWR Ground pin.
59 DIF_8 OUT 0.7V differential true clock output
60 DIF_8# OUT 0.7V differential Complementary clock output
61 DIF_9 OUT 0.7V differential true clock output
62 DIF_9# OUT 0.7V differential Complementary clock output
63 GND PWR Ground pin.
64 VDD PWR Power supply, nominal 3.3V
65 DIF_10 OUT 0.7V differential true clock output
66 DIF_10# OUT 0.7V differential Complementary clock output
67 DIF_11 OUT 0.7V differential true clock output
68 DIF_11# OUT 0.7V differential Complementary clock output
69 VDDIO PWR Power supply for differential outputs
70 GND PWR Ground pin.
71 ^OE10# IN
Active low input for enabling DIF pair 10. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
72 ^OE11# IN
Active low input for enabling DIF pair 11. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 5
9ZML1232 REV E 112015
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZML1232. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–DIF_IN Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA, R 4.6 V
1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
I/O Supply Voltage VDDIO 4.6 V
1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
TA = T
COM
; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
V
CROSS
Cross Over Voltage 150 900 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 6
9ZML1232 REV E 112015
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = T
COM
; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 25 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 -0.12 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 -0.02 200 uA 1
Input Frequency F
ib
yp
V
DD
= 3.3 V, Bypass mode 33 150 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
412clocks1
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Input Current
Capacitance
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
5
The differential input clock must be running for the SMBus to be active
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9ZML1232BKLF

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Buy 9ZML1232BKLF
Manufacturer:
IDT
Description:
Clock Buffer Buffer
Lifecycle:
New from this manufacturer.
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