9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
IDT®
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 8
9ZML1232 REV E 112015
Electrical Characteristics–Skew and Differential Jitter Parameters
TA = T
COM
; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] t
SPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-325 -225 -125 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
3 3.8 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50 0 50 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
-250 250 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DTE
Random Differential Tracking error beween two
9ZM devices in Hi BW Mode
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0] t
DSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZM devices in Hi BW Mode
75 ps 1,2,3,5,8
DIF{x:0] t
SKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
40 65 ps 1,2,3,8
PLL Jitter Peaking j
eak-hibw
LOBW#_BYPASS_HIBW = 1 0 2.5 dB 7,8
PLL Jitter Peaking j
eak-lobw
LOBW#_BYPASS_HIBW = 0 0 2 dB 7,8
PLL Bandwidth pll
HIBW
LOBW#_BYPASS_HIBW = 1 2 4 MHz 8,9
PLL Bandwidth pll
LOBW
LOBW#_BYPASS_HIBW = 0 0.7 1.4 MHz 8,9
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50.2 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-2 0.8 2 % 1,10
PLL mode 10 50 ps 1,11
Additive Jitter in Bypass Mode 0.1 50 ps 1,11
Notes for preceding table:
6.
t is the period of the input clock
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by desi
n and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mod
11
Measured from differential waveform
Jitter, Cycle to cycle t
jcyc-cyc
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4
This parameter is deterministic for a given device
5
Measured with scope averaging on to find mean value.
