MAX2140
Complete SDARS Receiver
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Detailed Description
Front End
The front end of the MAX2140, which downconverts the
RF signal to IF, is defined from the differential RF inputs
(pins RFIN+ and RFIN-) to the output (pins IFOUT+ and
IFOUT-) to the SAW filter.
The front end includes a self-contained analog RF AGC
loop. The engagement threshold of the loop can be
programmed from -35dBm to -15dBm referred to the
RF input in 1dB steps using the RF4–RF0 programming
bits. The time constant of the loop is set externally by
the capacitor connected to RFAGC_C.
The image reject first mixer ensures a good image and
half IF rejection.
The front-end gain can be reduced by programming
bits PM3–PM0 over a 22dB range, with a step of 2dB.
This allows the selections of SAW filters with different
insertion loss.
The IF output is nominally 900Ω differentially and requires
pullup inductors to V
CC
, which can be used as part of the
matching network to the SAW filter impedance.
Back End
The back end, which downconverts the IF signal to
quadrature baseband, is defined from the SAW filter
inputs (pins IFIN+ and IFIN-) to the baseband outputs
(pins IOUT+, IOUT-, QOUT+, QOUT-).
The back end contains an IF AGC loop, which is closed
by the baseband controller. The IF AGC control voltage
is applied at the AGCPWM pin. The gain can be
reduced over 53dB (typ) and exhibits a log-linear char-
acteristic.
The back end also contains individual lowpass filters on
each channel. The lowpass-filter bandwidth is the use-
ful SDARS downconverted bandwidth (6.25MHz). The
lowpass-filter performance is factory trimmed. The bit
IOT switches between the factory-trimmed set and the
control through the I
2
C-compatible bus using bits
B4–B1. Even when using the factory-trimmed set, the
user can still slightly modify the cutoff frequency (by
±250kHz) by varying bits LP1/LP0.
Highpass filters are also inserted in the back-end signal
paths. Their purpose is to remove the DC offset. They
are designed for a low corner frequency so as not to
degrade the SDARS content. Their exact cutoff frequen-
cy is set by the external capacitors connected between
IF2 access pins, given by the following equation:
f
cutoff
= 1/(2 x π x R x C) [Hz]
where R = 8000Ω, C = external capacitor to be
connected.
Finally, the HPF bit allows an increase to the back-end
gain by 4dB at the slight expense of a degraded in-
band linearity.
Frequency Generation
An on-chip VCO and a low-step fractional-N PLL
ensure the necessary frequency generation. The 1st
mixer’s LO is at the VCO frequency itself, while the 2nd
mixer’s LO is the VCO frequency divided by 4 or by 8
(bit D48). Hence, the two possible IF frequencies for
SDARS are 467MHz and 259MHz. Typical applications
are based on 259MHz IF frequency.
The reference divider path in the PLL can either use an
external crystal and the on-chip crystal oscillator or an
external TCXO that can overdrive the on-chip crystal
oscillator. A reference division ratio of 1 or 2 is set by
the REF bit. The crystal oscillator (or TCXO) signal is
available at pin REFOUT. The output is either at the
same frequency as the reference signal, or divided by
two, based on the setting of bit RFD.
The VCO main division ratio is set by bits N6–N0 (for
the integer part) and bits F19–F00 (for the fractional
part). The minimum step is below 30Hz, small enough
for effective AFC to be implemented by the baseband.
The charge-pump (pin CPOUT) is to be connected to
the VCO tuning input (pin VTUNE) through an appropri-
ate loop filter.
Overcurrent Protection
This DC function allows external circuitry consuming up
to 150mA and connected to the pin VOUTANT to sink
current from a V
CC
line (pin VINANT) through overcur-
rent-protection circuitry.
When no overcurrent is present, a low dropout voltage
exists between pins VINANT and VOUTANT. In over-
current conditions (including short-circuit from
VOUTANT to GND), the current is limited to approxi-
mately 300mA and bit ACP in the READ byte status
goes high.
This circuit also senses if the current drawn at the pin
VOUTANT is typically larger than 20mA, in which case
the bit AND from the READ byte status goes high (the
purpose is to inform the baseband controller if there is
any device drawing current from VOUTANT).
