10
COMMERCIAL TEMPERATURE RANGE
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
TABLE 3 — CONTROL REGISTER (CR) BITS
TABLE 4 — CONNECTION MEMORY BITS
Reset Value: 4000H.
Bit Name Description
15 Reset (Software Reset) A one will reset the device and have the same effect as of the RESET pin. Must be zero for normal operation.
14 O EI When 1, TX16-31/OEI0-15 will behave as OEI0-15. These outputs will reflect the active or high-impedance state of the corresponding
(Output Enable Indication) output data streams TX0-15. When 0, TX16-31/OEI0-15 will behave as TX16-31 and react in the same way as TX0-15.
13 OEPOL When 1, a one on OEI pin denotes an active state on the output data stream; zero on OEI pin denotes high-impedance state.
(Output Enable Polarity) When 0, a one denotes high-impedance and a zero denotes an active state.
12 AOE When 1, TX0-31 will behave as OEI0-31 accordingly. These outputs will reflect the active or high-impedance state of the
corresponding output data streams (TX0-31) in another IDT72V71643 if programmed identically.
11 MB P When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory high bits,
(Memory Block Program) bit 13 to bit 15. When 0, this feature is disabled.
10 Unused Must be zero for normal operation.
9-7 BPD2-0 These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature is
(Block Programming Data) activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents
of the bits BPD2-0 are loaded into bit 15 and 13 of the Connection Memory. Bit 12 to bit 0 of the Connection Memory are set to 0.
6 BPE A zero to one transition of this bit enables the memory block programming function. The BPE and BPD2-0 bits in the CR register
(Begin Block Programming have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the
Enable) block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed.
When the BPE=1, the other bit in the control register must not be changed for two frames to ensure proper operation.
5 OSB When ODE=0 and OSB=0, the output drivers of transmit serial streams are in high-impedance mode. When ODE=1 or OSB=1,
(Output Stand By) the output serial stream drivers function normally.
4 SFE A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero
(Start Frame Evaluation) to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one frame.
3-0 DR3-0 Input/Output data rate selection. See Table 5 for detailed programming.
1514131211109876543210
SRS OEI OEP AOE MBP 0 BPD2 BPD1 BPD0 BPE OSB SFE DR3 DR2 DR1 DR0
Bit Name Description
15 LPBK When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay
(Per Channel Loopback) offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This feature is offered only when
DR3-0 = 0000, 0001 or 0010 is selected via the control register.
14,13 MOD1-0
MOD1 MOD0 MODE
(Switching Mode Selection) 0 0 Variable Delay mode
0 1 Constant Delay mode
1 0 Processor mode
1 1 Output High-Impedance
12-8 SAB4-0 The binary value is the number of the data stream for the source of the connection. Unused SAB bits must be zero for proper
(Source Stream Address Bits) operation.
7-0 CAB7-0 The binary value is the number of the channel for the source of the connection. Unused CAB bits must be zero for proper
(Source Channel Address Bits) operation.
1514131211109876543210
LPBK MOD1 MOD0 SAB4 SAB3 SAB2 SAB1 SAB0 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
