©2011 Silicon Storage Technology, Inc. DS25040A 05/11
19
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Data Sheet
Microchip Technology Company
Figure 8: Toggle Bits Timing Diagram
Figure 9: WE# Controlled Chip-Erase Timing Diagram
1243 F06.1
ADDRESS A
MS-0
DQ
6
and DQ
2
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
1243 F07.1
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
AAA AAA AAA555 AAA
55 1055AA 80 AA
555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)
A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
