©2011 Silicon Storage Technology, Inc. DS25040A 05/11
6
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Data Sheet
Microchip Technology Company
timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or Block-
Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected
block will be ignored. During the command sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ
2
toggling and DQ
6
at “1”. While in Erase-Suspend mode, a Byte-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase
Resume command. The operation is executed by issuing one byte command sequence with Erase Resume com-
mand (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF168x provide a Chip-Erase operation, which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command
(10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Poll-
ing. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart.
Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-
Erase will be ignored. During the command sequence, WP# should be statically held high or low.
Write Operation Status Detection
The SST39VF168x provide two software means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle time. The software detection includes two sta-
tus bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the sys-
tem may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ
7
or DQ
6
.In
order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop
to read the accessed location an additional two (2) times. If both reads are valid, then the device has com-
pleted the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ
7
)
When the SST39VF168x are in the internal Program operation, any attempt to read DQ
7
will produce the
complement of the true data. Once the Program operation is completed, DQ
7
will produce true data. Note that
even though DQ
7
may have valid data immediately following the completion of an internal Write operation, the
remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent succes-
sive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ
7
will pro-
