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IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Functional Description
The IDT70V07 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V07 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFE (HEX), where a write is defined as CER = R/WR = VIL per Truth
Table III. The left port clears the interrupt through access of address
location 7FFE when CE
L = OEL = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INT
R) is asserted when the left port writes
to memory location 7FFF (HEX) and to clear the interrupt flag (INTR),
the right port must read the memory 7FFF location 7FFF. The
message (8 bits) at 7FFE or 7FFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations 7FFE and 7FFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the
interrupt operation.
programmed by tying the BUSY pins HIGH. If desired, unintended write
operations can be prevented to a port by tying the BUSY pin for that port
LOW.
The BUSY outputs on the IDT 70V07 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT70V07 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V07 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V07 is an extremely fast Dual-Port 32K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port SRAM or any other
shared resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
down feature controlled by CE, the Dual-Port SRAM enable, and SEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The busy pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V07 RAMs.
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MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
BUSY
L
BUSY
R
D
E
C
O
D
E
R
CE
CE
CE
