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70V07S35J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
7
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Test Conditions
Figure 1. AC Output Test Load
Timing of Power-Up Power-Down
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
CE
2943 drw 07
t
PU
I
CC
I
SB
t
PD
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2943 tbl 10
Figure 2. Output Test Load
(for t
LZ, tHZ, tWZ, tOW)
* Including scope and jig.
2943 drw 06
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
2943 drw 05
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC Read Cycle Time 25
____
35
____
55
____
ns
t
AA Address Access Time
____
25
____
35
____
55 ns
t
ACE Chip Enable Access Time
(3)
____
25
____
35
____
55 ns
t
AOE Output Enable Access Time
____
15
____
20
____
30 ns
t
OH Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ Output High-Z Time
(1,2)
____
15
____
20
____
25 ns
t
PU Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD Chip Disable to Power Down Time
(2)
____
25
____
35
____
50 ns
t
SOP Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
15
____
ns
t
SAA Semaphore Address Access Time
____
35
____
45
____
65 ns
2943 tbl 11
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual t
DH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
t
RC
R/W
CE
ADDR
t
AA
OE
2943 drw 08
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
Symbol Parameter
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 25
____
35
____
55
____
ns
t
EW
Chip Enable to End-of-Write
(3)
20
____
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 20
____
25
____
40
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
20
____
30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
20
____
25 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
20
____
25 ns
t
OW
Output Active from End-of-Write
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2943 tbl 12
9
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4)
(4)
(3)
2943 drw 09
(7)
(9)
(7)
t
LZ
,
t
HZ
(7)
2943 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
(3)
(2)
(6)
CE or SEM
(9)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

70V07S35J

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Buy 70V07S35J
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Description:
SRAM 32Kx8, 256K, 3.3V DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
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