1. General description
The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs,
D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly
from the internal registers. Data on the A or B bus is clocked in the internal registers, as
the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE
)
and direction (DIR) inputs are provided to control the transceiver function. In the
transceiver mode, data present at the high-impedance port may be stored in either the A
or B register, or in both. With the select source inputs (SAB and SBA), stored and
real-time (transparent mode) data can be multiplexed. The direction (DIR) input
determines which bus receives data when OE
is active (LOW). In the isolation mode (OE
= HIGH), A data may be stored in the B register and/or B data may be stored in the A
register. When an output function is disabled, the input function is still enabled and may be
used to store and transmit data. Only one of the two buses A or B may be driven at a time.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Supports partial power-down applications; inputs/outputs are high-impedance when
V
CC
=0V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85C and 40 Cto+125C.
74LVC646A
Octal bus transceiver/register; 3-state
Rev. 5 — 28 March 2013 Product data sheet
74LVC646A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 28 March 2013 2 of 23
NXP Semiconductors
74LVC646A
Octal bus transceiver/register; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC646AD 40 Cto+125C SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74LVC646ADB 40 Cto+125C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74LVC646APW 40 Cto+125C TSSOP24 plastic thin shrink small outline package;
24 leads; body width 4.4 mm
SOT355-1
Fig 1. Functional diagram
B0 204A0
B1 195A1
B2 186A2
B3 177A3
B4 168A4
B5 159A5
OE
DIR
SAB
SBA
CPAB
CPBA
B6 1410 A6
B7 1311 A7
23
1
22
2
3
21
001aab042
74LVC646A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 28 March 2013 3 of 23
NXP Semiconductors
74LVC646A
Octal bus transceiver/register; 3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
3
4
5
6
7
8
9
10
11
1
2
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
OE
21
B0
B1
B2
B3
B4
B5
B6
B7
CPBA
SBA
23
22
20
19
18
17
16
15
14
13
001aab040
3EN2
3EN1
4
001aab041
6
3
1
G6
G7
22
2
C5
G3
1
21
C4
23
6
1
4D
1
5D
1
7
1
7
2
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13

74LVC646ADB,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 3.6V 24SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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