74LVC646A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 28 March 2013 4 of 23
NXP Semiconductors
74LVC646A
Octal bus transceiver/register; 3-state
Fig 4. Logic diagram
001aab043
DIR
OE
SBA
CPBA
SAB
CPAB
Y
MUX
D
1
D
2
S
Q
FF
n
D
CP
Bn
V
CC
Y
MUX
D
1
D
2
S
Q
FF
n
D
CP
V
CC
An
8 identical channels
74LVC646A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 28 March 2013 5 of 23
NXP Semiconductors
74LVC646A
Octal bus transceiver/register; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SO24 and (T)SSOP24
646A
CPAB V
CC
SAB CPBA
DIR SBA
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
001aab039
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
Table 2. Pin description
Symbol Pin Description
CPAB 1 A to B clock input (LOW to HIGH; edge-triggered)
SAB 2 A to B select source input
SBA 22 B to A select source input
DIR 3 direction control input
A[0:7] 4, 5, 6, 7, 8, 9, 10, 11 A data input/output
B[0:7] 20, 19, 18, 17, 16, 15, 14, 13 B data input/output
OE
21 output enable input (active LOW)
CPBA 23 B to A clock input (LOW to HIGH, edge-triggered)
GND 12 ground (0 V)
V
CC
24 supply voltage
74LVC646A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 28 March 2013 6 of 23
NXP Semiconductors
74LVC646A
Octal bus transceiver/register; 3-state
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW to HIGH level transition
[2] The data output functions are enabled or disabled by various signals at the OE
and DIR inputs. Data input functions are always enabled,
i.e. data at the bus inputs are stored on every LOW to HIGH transition on the clock inputs.
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO24 packages: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP24 packages: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
Table 3. Function table
[1]
Input Data I/O Function
OE DIR CPAB CPBA SAB SBA A0 to A7 B0 to B7
XX X X X input unspecified
[2]
store A and B unspecified
XXX X X unspecified
[2]
input store B and A unspecified
HXX X input input store A and B data
H X H or L H or L X X input input hold storage; isolation
L L X X X L output input real-time B data to A bus
L L X H or L X H output input stored B data to A bus
L H X X L X input output real-time A data to B bus
L H H or L X H X input output stored A data to B bus
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
<0V 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
>V
CC
or V
O
<0V - 50 mA
V
O
output voltage output HIGH or LOW state
[2]
0.5 V
CC
+0.5 V
output 3-state
[2]
0.5 +6.5 V
I
O
output current V
O
=0V toV
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
- 500 mW

74LVC646ADB,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 3.6V 24SSOP
Lifecycle:
New from this manufacturer.
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