DS1993L-F5+ Datasheet DS1993L-F5+, DS1992L-F5+ | P13-P15

DS1992/DS1993

13 of 17

Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE

RESISTOR

MASTER

DS199x

MASTER RX "PRESENCE PULSE"

480 µs

≤

t

RSTL

<

∞

*

480 µs

≤

t

RSTH

<

∞

**

15 µs

≤

t

PDH

< 60 µs

60

≤

t

PDL

< 240 µs

MASTER T

X

"RESET PULSE"

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

t

RSTH

t

RSTL

t

PDH

t

PDL

t

R

* In order not to mask interrup signaling

by other devices on the 10Wire bus t

RSTL

+ t

R

should always be less than 960 us

** Includes recovery time

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line

low initiates all time slots. The falling edge of the data line synchronizes the DS199x to the master by

triggering a delay circuit in the DS199x. During write time slots, the delay circuit determines when the

DS199x samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit

determines how long the DS199x holds the data line low overriding the 1 generated by the master. If the

data bit is a 1, the iButton leaves the read data time slot unchanged.

Figure 11. READ/WRITE TIMING DIAGRAM

Write-One Time Slot

15µs

60µs

DS199x

Sampling Window

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

t

SLOT

t

REC

t

LOW1

60 µs

≤

t

SLOT

< 120 µs

1 µs

≤

t

LOW1

< 15 µs

1 µs

≤

t

REC

<

∞

RESISTOR

MASTER

DS1992/DS1993

14 of 17

Figure 11. READ/WRITE TIMING DIAGRAM (continued)

Write-Zero Time Slot

15µs

RESISTOR

MASTER

DS199x

60µs

t

LOW0

Sampling Window

60 µs

≤

t

LOW0

< t

SLOT

< 120 µs

1 µs

≤

t

REC

<

∞

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

t

SLOT

t

REC

Read-Data Time Slot

RESISTOR

MASTER

DS199

x

Master

Sampling Window

60 µs

≤

t

SLOT

< 120 µs

1 µs

≤

t

LOWR

< 15 µs

0

≤

t

RELEASE

< 45 µs

1 µs

≤

t

REC

<

∞

t

RDV

= 15 µs

t

SU

< 1 µs

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

t

SLOT

t

REC

t

LOWR

t

SU

t

RDV

t

RELEASE

DS1992/DS1993

15 of 17

PHYSICAL SPECIFICATIONS

Size See mechanical drawing

Weight 3.3 grams (F5 package)

Expected Service Life 10 years at +25°C

Safety Meets UL 913, 5th Ed., Rev. 1997-02-24; Intrinsically Safe

Apparatus, Approved under Entity Concept for use in

Class I, Division 1, Group A, B, C, and D Locations

ABSOLUTE MAXIMUM RATINGS

Voltage Range on any Pin Relative to Ground -0.5V to +7.0V

Operating Temperature Range -40°C to +70°C

Storage Temperature Range -40°C to +70°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect

reliability.

DC ELECTRICAL CHARACTERISTICS

(T

A

= -40°C to +70°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

1-Wire Pullup Voltage

(Notes 1, 3)

V

PUP

2.8 6.0 V

Logic 1 (Notes 1, 2)

V

IH

2.2

V

Logic 0 (Note 1)

V

IL

-0.3

+0.3

V

Output Logic Low at 4mA

(Note 1)

V

OL

0.4 V

Input Load Current (Note 4)

I

L

5

µA

CAPACITANCE

(T

A

= +25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

I/O (1-Wire) (Notes 5, 6)

C

IN/OUT

100

800

pF

AC ELECTRICAL CHARACTERISTICS

(V

PUP

= 2.8V to 6.0V, T

A

= -40°C to +70°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Time Slot

t

SLOT

60

120

µs

Write 1 Low Time

t

LOW1

1

15

µs

Write 0 Low Time

t

LOW0

60

120

µ

s

Read Data Valid

t

RDV

exactly 15

µ

s

Release Time

t

RELEASE

0

15

45

µs

Read Data Setup (Note 7)

t

SU

1

µs

Recovery Time

t

REC

1

µs

Reset Time High (Note 8)

t

RSTH

480

µ

s

Reset Time Low (Note 9)

t

RSTL

480 960

µ

s

Presence Detect High

t

PDH

15 60

µ

s

Presence Detect Low

t

PDL

60

240

µ

s

DS1993L-F5+

DS1993L-F5+

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