AD7457
Rev. A | Page 9 of 20
V
REF
(V)
CHANGE IN DNL (LSB)
4.0
3.5
2.5
3.0
1.5
1.0
2.0
0.5
0
0.5
1.0
01.00.5 1.5 3.02.52.0 3.5
POSITIVE DNL
NEGATIVE DNL
03157-0-020
Figure 11. Changes in DNL vs. V
REF
for V
DD
= 5 V
V
REF
(V)
CHANGE IN INL (LSB)
5
4
3
1
2
0
1
2
01.00.5 1.5 3.02.52.0 3.5
POSITIVE INL
NEGATIVE INL
03157-0-021
Figure 12. Change in INL vs. V
REF
for V
DD
= 5 V
V
REF
(V)
EFFECTIVE NUMBER OF BITS (LSB)
12
11
10
8
9
7
6
01.00.5 1.5 3.02.52.0 3.5
V
DD
= 3V
V
DD
= 5V
03157-0-022
Figure 13. ENOB vs. V
REF
for V
DD
= 3 V and 5 V
AD7457
Rev. A | Page 10 of 20
TERMINOLOGY
Signal to (Noise + Distortion) Ratio (SINAD)
The measured ratio of SINAD at the output of the ADC. The
signal is the rms amplitude of the fundamental. Noise is the
sum of all nonfundamental signals up to half the sampling
frequency (f
S
/2), excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process; the
more levels, the smaller the quantization noise. The theoretical
SINAD ratio for an ideal N-bit converter with a sine wave input
is given by
(
)
(
)
dB76.102.6 +=+ NDistortionNoisetoSignal
Therefore, for a 12-bit converter, the SINAD is 74 dB.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7457, it is defined as
()
1
2
6
2
5
2
4
2
3
2
2
20dB
V
VVVVV
logTHD
++++
=
where:
V
1
is the rms amplitude of the fundamental.
V
2
, V
3
, V
4
, V
5
, and V
6
are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f
S
/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specifica-
tion is determined by the largest harmonic in the spectrum, but,
for ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion prod-
ucts at sum and difference frequencies of mfa ± nfb, where m, n
= 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and
(fa − 2fb).
The AD7457 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in fre-
quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
total harmonic distortion specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dB.
Aperture Delay
The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the actual sample is taken.
Full-Power Bandwidth
The full-power bandwidth of an ADC is that input frequency
at which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (000...000 to 000...001)
from the ideal (that is, AGND + 1 LSB).
Gain Error
The deviation of the last code transition (111...110 to 111...111)
from the ideal (that is, V
REF
− 1 LSB), after the offset error has
been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within
0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC V
DD
supply of frequency fs. The frequency of this
input varies from 1 kHz to 1 MHz.
PSRR(dB) = 10 log(Pf/Pfs)
Pf
is the power at frequency f in the ADC output; Pfs is the
power at frequency
fs in the ADC output.
AD7457
Rev. A | Page 11 of 20
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7457 is a 12-bit, low power, single supply, successive
approximation analog-to-digital converter (ADC) with a
pseudo differential analog input. It operates with a single 2.7 V
to 5.25 V power supply and is capable of throughput rates up to
100 kSPS. It requires an external reference to be applied to the
V
REF
pin.
The AD7457 has an on-chip differential track-and-hold
amplifier, a successive approximation (SAR) ADC, and a serial
interface housed in an 8-lead SOT-23 package. The serial clock
input accesses data from the part and provides the clock source
for the successive approximation ADC. The AD7457 automati-
cally powers down after conversion, resulting in low power
consumption.
CONVERTER OPERATION
The AD7457 is a successive approximation ADC based around
two capacitive DACs. Figure 14 and Figure 15 show simplified
schematics of the ADC in the acquisition phase and the conver-
sion phase, respectively. The ADC is comprised of control logic,
a SAR, and two capacitive DACs. In Figure 14 (acquisition
phase), SW3 is closed, SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
V
IN+
V
IN
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
C
S
C
S
V
REF
SW2
B
A
03157-0-003
Figure 14. ADC Acquisition Phase
When the ADC starts a conversion (Figure 15), SW3 opens, and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC’s output code. The output impedances of the sources
driving the V
IN+
and the V
IN–
pins must be matched; otherwise
the two inputs have different settling times, resulting in errors.
V
IN+
V
IN
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
C
S
C
S
V
REF
SW2
B
A
03157-0-004
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7457 is straight (natural) binary.
The designed code transitions occur at successive LSB values
(1 LSB, 2 LSB, and so on). The LSB size is V
REF
/4096. The ideal
transfer characteristics of the AD7457 are shown in Figure 16.
000...00
0V
ADC CODE
ANALOG INPUT
111...11
000...01
111...00
011...11
1LSB
V
REF
1LSB
1LSB = V
REF
/4096
111...10
000...10
03157-0-005
Figure 16. Ideal Transfer Characteristics
TYPICAL CONNECTION DIAGRAM
Figure 17 shows a typical connection diagram for the AD7457.
In this setup, the GND pin is connected to the analog ground
plane of the system. The V
REF
pin is connected to the AD780,
a 2.5 V decoupled reference source. The signal source is
connected to the V
IN+
analog input via a unity gain buffer. A
dc voltage is connected to the V
IN–
pin to provide a pseudo
ground for the V
IN+
input. The V
DD
pin should be decoupled to
AGND with a 10 µF tantalum capacitor in parallel with a 0.1 µF
ceramic capacitor. The reference pin should be decoupled to
AGND with a capacitor of at least 0.33 µF. The conversion result
is output in a 16-bit word with four leading zeros followed by
the MSB of the 12-bit result.

AD7457BRTZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit P/Diff Input 100KSPS
Lifecycle:
New from this manufacturer.
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