OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7457BRTZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7457
Rev. A | Page 3 of 20
SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 100 kSPS, V
REF
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments B Version
1
Unit
DYNAMIC PERFORMANCE f
IN
= 30 kHz
Signal to Noise Ratio (SNR)
2
71 dB min
Signal to (Noise + Distortion) (SINAD)
2
70 dB min
Total Harmonic Distortion (THD)
2
−84 dB typ −75 dB max
Peak Harmonic or Spurious Noise
2
−86 dB typ −75 dB max
Intermodulation Distortion (IMD)
2
fa = 25 kHz; fb = 35 kHz
Second-Order Terms −80 dB typ
Third-Order Terms −80 dB typ
Aperture Delay
2
5 ns typ
Aperture Jitter
2
50 ps typ
Full-Power Bandwidth
2, 3
@ −3 dB 20 MHz typ
@ −0.1 dB 2.5 MHz typ
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)
2
±1 LSB max
Differential Nonlinearity (DNL)
2
Guaranteed no missed codes to 12 bits ±0.95 LSB max
Offset Error
2
±4.5 LSB max
Gain Error
2
±2 LSB max
ANALOG INPUT
Full-Scale Input Span
V
IN+
− V
IN−
V
REF
V
Absolute Input Voltage
V
IN+
V
REF
V
V
IN−
4
V
DD
= 2.7 V to 3.6 V −0.1 to +0.4 V
V
DD
= 4.75 V to 5.25 V −0.1 to +1.5 V
DC Leakage Current ±1 µA max
Input Capacitance When in track/hold 30/10 pF typ
REFERENCE INPUT
V
REF
Input Voltage
5
±1% tolerance for specified performance 2.5 V
DC Leakage Current ±1 µA max
V
REF
Input Capacitance When in track/hold 10/30 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
IN
Typically 10 nA, V
IN
= 0 V or V
DD
±1 µA max
Input Capacitance, C
IN
6
10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
= 4.75 V to 5.25 V, I
SOURCE
= 200 µA 2.8 V min
V
DD
= 2.7 V to 3.6 V, I
SOURCE
= 200 µA 2.4 V min
Output Low Voltage, V
OL
I
SINK
= 200 µA 0.4 V max
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance
6
10 pF max
Output Coding Straight natural binary
CONVERSION RATE
Conversion Time 1.6 µs with a 10 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time
2
1 µs max
Throughput Rate See the Serial Interface section 100 kSPS max
AD7457
Rev. A | Page 4 of 20
Parameter Test Conditions/Comments B Version
1
Unit
POWER REQUIREMENTS
V
DD
2.7/5.25 V min/max
I
DD
7, 8
During Conversion
6
V
DD
= 4.75 V to 5.25 V 1.5 mA max
V
DD
= 2.7 V to 3.6 V 1.2 mA max
Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) V
DD
= 4.75 V to 5.25 V 0.7 mA max
V
DD
= 2.7 V to 3.6 V 0.33 mA max
Power-Down SCLK on or off 1 µA max
Power Dissipation
Normal Mode (Operational) V
DD
= 5 V 3 mW max
V
DD
= 3 V 0.9 mW max
Power-Down V
DD
= 5 V; SCLK on or off 5 µW max
V
DD
= 3 V; SCLK on or off 3 µW max
1
Temperature range for B version: −40°C to +85°C.
2
See the section. Terminology
3
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4
A dc input is applied to V
IN–
to provide a pseudo ground for V
IN+
.
5
The AD7457 is functional with a reference input range of 100 mV to V
DD
.
6
Guaranteed by characterization.
7
See the section. Power Consumption
8
Measured with a full-scale dc input.
AD7457
Rev. A | Page 5 of 20
TIMING SPECIFICATIONS
1
V
DD
= 2.7 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 100 kSPS, V
REF
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
2
10 kHz min
10 MHz max
t
CONVERT
16 × t
SCLK
t
SCLK
= 1/f
SCLK
1.6 µs max
t
2
10 ns min
CS
rising edge to SCLK falling edge setup time
t
3
3
20 ns max
Delay from
CS
rising edge until SDATA three-state disabled
t
4
3
40 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK high pulse width
t
6
0.4 t
SCLK
ns min SCLK low pulse width
t
7
10 ns min SCLK edge to data valid hold time
t
8
4
10 ns min SCLK falling edge to SDATA three-state enabled
35 ns max SCLK falling edge to SDATA three-state enabled
t
POWER-UP
5
1 µs max Power-up time from full power-down
t
POWER-DOWN
7.4 µs min Minimum time spent in power-down
1
The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V. See and the Serial section. Figure 2 Interface
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3
Figure 3.
DD
= 5 V, and the time required for the output to
cross 0.4 V or 2.0 V for V
DD
= 3 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5
See the section. Power Consumption
0 0 0 DB11 DB10 DB2 DB1 DB00
t
4
t
6
t
7
t
8
t
3
T
POWERDOWN
THREE-STATE
AUTOMATIC
POWER DOWN
T
POWERUP
T
ACQUISITION
POWER
UP
CONVERT
START
TRACK TRACK
T
ACQUISTION
T
POWERUP
4 LEADING ZEROS
SDAT
A
SCLK
CS
THREE-STATE
t
2
t
5
03157-0-001
HOLD
Figure 2. AD7457 Serial Interface Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7457BRTZ-REEL7

Mfr. #:
Buy AD7457BRTZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit P/Diff Input 100KSPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet