AD7457
Rev. A | Page 15 of 20
Table 5. SPORT0 Configuration
Bit Setting Comment/Description
ISCLK 1 Serial clock is generated internally
SLEN 1111 16 bits of conversion data
RFSR 0 Receive frame sync required every word
TFSR Don’t care Not used
IRFS 0
RFS is set to be an input and is
generated externally.
ITFS Don’t care Not used
RFSW 1 Alternate receive framing
TFSW Don’t care Not used
INVRFS 0 RFS is active high
INVTFS Don’t care Not used
SPORT0 is configured by setting the bits in its control register,
as listed in Table 5.
The flag to generate the
CS
signal is generated by SPORT1. It is
connected to both the ADC and the RFS input of SPORT0 to
provide the frame sync signal for the DSP.
AD7457
Rev. A | Page 16 of 20
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7457 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes, because it
gives the best shielding. Digital and analog ground planes
should be joined in only one place, and the connection should
be a star ground point established as close as possible to the
GND pin on the AD7457.
Avoid running digital lines under the device, because this
couples noise onto the die. The analog ground plane should be
allowed to run under the AD7457 to avoid noise coupling. The
power supply lines to the AD7457 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals,
such as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feed through the board. A micro strip technique is the best,
but is not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, place them as close as possible to
the device.
AD7457
Rev. A | Page 17 of 20
OUTLINE DIMENSIONS
13
56
2
8
4
7
2.90 BSC
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.22
0.08
0.60
0.45
0.30
2.80 BSC
PIN 1
INDICATO
R
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 26. 8-Lead Small Outline Transistor Package [SOT-23]
(RT-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Linearity Error (LSB)
1
Package Description Package Option Branding
AD7457BRT-R2 –40°C to +85°C ±1 8-Lead SOT-23 RT-8 COJ
AD7457BRT-REEL7 –40°C to +85°C ±1 8-Lead SOT-23 RT-8 COJ
AD7457BRTZ-REEL7
2
–40°C to +85°C ±1 8-Lead SOT-23 RT-8 COD
1
Linearity error here refers to integral nonlinearity error.
2
Z = Pb-free part.

AD7457BRTZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit P/Diff Input 100KSPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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