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NCP1028P065G

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NCP1028
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19
Designing the Auxiliary Winding
A NCP1028 internal arrangement clamps the voltage
applied on the V
CC
pin. It uses an active shunt circuitry as
shown on Figure 33. Care must be taken to avoid injecting
too much current when the clamp is activated. The
insertion of a resistor (R
limit
) between the auxiliary dc level
and the V
CC
pin is thus mandatory not to damage the
internal 8.7 V zener diode during an overshoot for instance
(absolute maximum current is 15 mA. Please note that
there cannot be bad interaction between the clamping
voltage of the internal zener and VCC
ON
since this
clamping voltage is actually built on top of VCC
ON
with a
fixed amount of offset (200 mV typical). R
limit
should be
carefully selected to avoid disturbing the V
CC
in low / light
load conditions. The below lines detail how to evaluate the
R
limit
value.
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a
SMPS operated at nominal load can deliver an auxiliary
voltage of an arbitrary 16 V (V
nom
), this voltage can drop
below 10 V (V
stby
) when entering standby. This is because
the recurrence of the switching pulses expands so much that
the low frequency re−fueling rate of the V
CC
capacitor is
not enough to keep a proper auxiliary voltage. Figure 34
portrays a typical scope shot of a SMPS entering deep
standby (output un−loaded). Thus, care must be taken when
calculating R
limit
not to drop too much voltage over it when
entering standby. Otherwise, the converter will enter burst
mode as it will sense an UVLO condition. Based on these
recommendations, we are able to bound
R
limit
between two
equations:
(eq. 3)
V
nom
−V
clamp
I
CCmax
v R
limit
v
V
stby
−V
CCON
ICC1
Where:
V
nom
is the auxiliary voltage at nominal load.
V
stdby
is the auxiliary voltage when standby is entered.
ICC
max
is the maximum current you can inject in the pin
without damaging the controller (15 mA).
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part
in standby does almost not switch. It is around 1.0 mA for
the 65 kHz version and 1.4 mA for the 100 kHz one.
VCC
(min)
is the level above which the auxiliary voltage
must be maintained to keep the controller away from the
UVLO trip point. It is good to obtain around 8.0 V in order
to offer an adequate design margin, e.g. to not reactivate the
startup source (which is not a problem in itself if low
standby power does not matter).
←
+
-
+
-
+
V
CCON
= 8.5 V
V
CC(min)
= 7.5 V
Startup
Source
Drain
+
V
clamp
= 8.7 V Typ.
I > 6 mA
Ground
V
CC
+
C
VCC
+
C
AUX
L
aux
R
limit
D1
Figure 33. A more detailed view of the NCP1028 offers better
insight on how to properly wire an auxiliary winding.
Since R
limit
shall not bother the controller in standby, e.g.
keep V
auxiliary
to around 8.0 V (as selected above), we
purposely select a V
nom
well above this value. As explained
before, experience shows that a 40% decrease can be seen
on auxiliary windings from nominal operation down to
standby mode. Let’s select a nominal auxiliary winding of
20 V to offer sufficient margin regarding 8.0 V when in
standby (R
limit
also drops voltage in standby…).
Plugging the values in Equation 3 gives the limits within
which R
limit
shall be selected:
20−8.7
10 m
v R
limit
v
12−8
1m
, that is say : 1.3 kW t R
limit
t 4kW.
to
We purposely limited the injected current to 10 mA in
order to include a safety margin.
NCP1028
www.onsemi.com
20
Figure 34. The burst frequency becomes so low
that it is difficult to keep an adequate level on the
auxiliary V
CC
.
> 30 ms
Over Power Compensation
Over Power Compensation or Protection (OPP)
represents a way to limit the effects of the propagation
delay when the converter is supplied from its highest input
voltage. The propagation delay naturally extends the
power capability of any current−limited converter.
Figure 35 explains why. The main parameter is the on
slope, that is to say, the pace at which the inductor current
grows−up when the power switch closes. For a flyback
controller, the slope is given by:
S
on
+
V
in
L
p
(eq. 4)
where L
p
is the transformer magnetizing/primary
inductance and V
in
, the input voltage.
Figure 35. Internal logic blocks take a certain
amount of time before shutting off the driving
pulses in presence of an overcurrent event.
As the internal logic takes some time to react, the switch
gate shutdown does not immediately occur when the
maximum power limit is detected (just before activating
the overload protection circuit). Clearly speaking, it can
take up to 100 ns for the NCP1028 current sense
comparator to propagate through the various logical gates
before reaching the power switch and finally shutting it off.
This is the well−known propagation delay noted
t
prop
.
Unfortunately, during this time, the current keeps growing
as Figure 35 depicts. The peak current will therefore be
troubled by this propagation delay. The formula to obtain
the final value is simply:
I
peak,final
+
V
in
L
p
t
(eq. 5)
) I
peak,max
prop
At low line, S
on
is relatively low and does not bother the
final peak value. The situation differs at high line and
induces a higher peak current. Therefore, the power supply
output power capability increases with the input voltage.
Let us a take a look at a simple example. Suppose the peak
current is 700 mA:
L
p
= 1.0 mH
V
in
lowline = 100 Vdc
V
in
highline = 350 Vdc
I
peak,max
= 700 mA
t
prop
= 100 ns
P
out
+
1
2
I
2
peak,final
F
SW
L
p
h
(eq. 6)
Where: F
sw
is the switching frequency and h the efficiency.
Usually h is bigger in high line conditions than in low line
conditions. This formula is valid for a Discontinuous
Conduction Mode flyback.
From Equation 5, we can calculate the final peak current
in both conditions:
I
peak,final
= (100/1m) x 100n + 700m = 710 mA at low line.
I
peak,final
= (350/1m) x 100n + 700m = 735 mA at high line.
From Equation 6, we can have an idea of the maximum
output power capability again, in both conditions with
respective low and high line efficiency numbers of 78%
and 82% for instance:
P
out,lowline
= 0.5 0.71
2
1m 65k 0.78 = 12.8 W
P
out,highline
= 0.5 0.735
2
1m 65k 0.82 = 14.4 W
NCP1028
www.onsemi.com
21
This difference might not be seen as a problem, but some
design specifications impose stringent conditions on the
maximum output current capability, regardless the line
input. Hence the need for an OPP input…
Since we want to limit the power to 12.8 W at high line,
let us calculate the needed peak current:
From equation 6: I
peak
+
2P
out
F
SW
L
p
h
Ǹ
= 693 mA to
deliver 12.8 W at high line.
Compared to our 735 mA, we need to decrease the
setpoint by 6% roughly when V
in
equals 350 Vdc.
The NCP1028 hosts a special circuitry looking at the
couple voltage/current present on pin 7. Figure 36 shows
how to arrange components around the controller to obtain
Over Power Protection.
Current
Setpoint
Over Power
Protection
OPP
Bulk
ROPPU
ROPPL
GND
Figure 36. A resistive network reduces the
power capability in high−line conditions.
First, you need to know the required injected current and
the voltage across pin 7 to start activating OPP.
Experiments consist in wiring Figure 36 circuit and
running the power supply in conditions where it must shut
down (e.g. highest input voltage and maximum output
current per specification). For this, R
OPPL
can be put to
10 kW and R
OPPU
made of a series string of 4 1.0 MW
resistors plus a 10−turn 1.0 MW potentiometer set at its
maximum value. An amp−meter is inserted in series with
pin 7 and a volt−meter monitors its voltage with respect to
ground. Once the power supply is powered, slowly rotate
the potentiometer and observe both voltage and current
going up at pin 7. At a certain time, as voltage and current
increase, the controller will shut down the power supply.
The current at this time is the one we are looking for.
Suppose these experiments lead to 80 mA with a pin 7
activation voltage of 2.45 V. Final resistor equations are:
VbulkH = 375 Vdc ; the maximum voltage at which OPP
must shut down the controller
V
bulkL
= 200 Vdc ; the minimum voltage below which
OPP is not activated
I
OPP
= 80 mA ; the current in pin 7
V
f
= 2.45 V ; the voltage of pin 7 at the above
condition
R
OPPL
+
V
bulkH
−V
bulkL
I
OPP
(V
bulkL
−V
f
)
V
f
+ 27 kW
(eq. 7)
R
OPPH
+ R
OPPL
V
bulkL
−V
f
V
f
+ 2.2 MW
(eq. 8)
If the OPP feature is not needed for some designs, it is
possible to ground it via a copper wire to the adjacent
ground pin. This can help to develop a larger copper area
in an application where the thermal resistance is an
important parameter.
Ramp Compensation
When operating in Continuous Conduction Mode
(CCM), current−mode power supplies can exhibit
so−called sub−harmonic oscillations. To cure this problem,
the designer must inject ramp compensation. The ramp can
either be added to the current sense information or directly
subtracted from the feedback signal. Figure 37 details the
internal arrangement of the ramp compensation circuitry.
Gate Reset
Ramp
RR
Vp
V
DD
IRR
Control
Figure 37. The Internal Feedback Chain and the Ramp Compensation Network
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NCP1028P065G

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Buy NCP1028P065G
Manufacturer:
ON Semiconductor
Description:
AC/DC Converters NCP1028 65 KHZ
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