NCP1028
www.onsemi.com
22
The principle consists in selecting the RR resistor,
connected from pin 2 to ground, to impose a current I
RR
in
the transistor collector.
Figure 38. Maximum Peak Current Setpoint
Variations versus Ramp Compensation
The equation to get the right compensation level is the
following:
RR +
V
p
2.75 k
S
a
@T
SW
(eq. 9)
where Vp, the total voltage swing, equals 2.75 V.
Application example:
Suppose we have the following flyback specifications:
Vout = 5.0 V output voltage
Vf = 1.0 V secondary diode forward drop
@ Iout nominal
Np:Ns = 1:N = 1:0.052 transformer turn ratio
Lp = 3.8 mH primary inductance
We can calculate the off slope, the one actually needed
to evaluate S
a
, by reflecting the output voltage over the
primary inductance. The slope is projected over a complete
switching period. Here, we use a 65 kHz part.
S
off
+
V
out
)
V
f
NL
p
T
SW
+
6 15u
0.052 3.8m
+ 455 mAń15 m
s
(eq. 10
)
Due to the internal sense arrangement, this current slope
will become a voltage slope having a value of:
SȀ
off
+ 455m 0.375 + 170 mVń15 ms
(eq. 11)
If we chose 50% of this downslope, then the final
compensation ramp will present a slope of:
S
a
+
170m
2
+ 85 mVń15 ms
(eq. 12)
We then have:
RR +
V
p
2.75 k
S
a
@T
SW
+
2.75 2.75k
85m
+ 89 kW
(eq. 13)
In the above calculations, the internal ESD resistor has
purposely been omitted to avoid bringing in another
variable. In case no ramp compensation is required, pin 2
must be tied to V
CC
, the adjacent pin.
Soft−Start
The NCP1028 features a 1.0 ms soft−start, which
reduces the power−on stress, but also contributes to lower
the output overshoot. Figure 39 shows a typical operating
waveform. The NCP1028 features a novel patented
structure which offers a better soft−start ramp, almost
ignoring the startup pedestal inherent to traditional
current−mode supplies.
Figure 39. 1.0 ms Soft−Start Sequence
NCP1028
www.onsemi.com
23
Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The NCP1028 offers a "6%
deviation of the nominal switching frequency. The sweep
sawtooth is internally generated and modulates the clock
up and down with a fixed frequency of 300 Hz. Figure 40
shows the relationship between the jitter ramp and the
frequency deviation. It is not possible to externally disable
the jitter.
65kHz
68.9kHz
61.1kHz
Jitter ramp
Internal
sawtooth
adjustable
Figure 40. Modulation Effects on the Clock Signal by the
Jittering Sawtooth
Skip−Cycle
Skip cycle offers an efficient way to reduce the standby
power by skipping unwanted cycles at light loads.
However, the recurrent frequency in skip often enters the
audible range and a high peak current obviously generates
acoustic noise in the transformer. The noise takes its origins
in the resonance of the transformer mechanical structure
which is excited by the skipping pulses. A possible
solution, successfully implemented in the NCP1200 series,
also authorizes skip cycle but only when the power demand
as dropped below a given level. This is what Figure 41
shows, as implemented on the NCP1028.
0
Skip cycle
current limit
Nominal peak
current
Figure 41. Low Peak Current Skip Cycle Guarantees Noise−Free Operation
NCP1028
www.onsemi.com
24
5.0 V/3.0 A Universal Mains Power Supply
Due to its low R
DS(on)
, the NCP1028 can be used in
universal mains SMPS up to 15 W of continuous power,
provided that the chip power dissipation is well under
control. That is to say that average power calculations and
measurements have been carried and correlated. The
design of an SMPS around a monolithic device does not
differ from that of a standard circuit using a controller and
a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices. Let us
follow the steps:
V
in
min = 120 Vdc
V
in
max = 375 Vdc
V
out
= 5.0 V
V
out
= 15 W
Operating mode is CCM
h = 0.8
1. The lateral MOSFET body−diode shall never be
forward biased, either during startup (because of a
large leakage inductance) or in normal operation
as shown by Figure 42. This condition sets the
maximum voltage that can be reflected during t
off
.
1.004M 1.011M 1.018M 1.025M 1.032M
50.0
50.0
150
250
350
> 0 !!
Figure 42. The reflected voltage shall always be greater
than the minimum input voltage to avoid the forward
biasing of the MOSFET body−diode.
Figure 43. Primary Inductance Current
Evolution in CCM
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N(V
out
) V
f
) t V
in, min
t Vin
min
(eq. 14)
. In our case,
since we operate from a 120 V DC rail while delivering
5.0 V, we can select a reflected voltage of 110 V
DC maximum: 120−110 > 0. Therefore, the turn ratio
Np:Ns must be smaller than
V
in
V
out
) V
f
+
110
5 ) 1
+ 18.3 or
Np : Ns t 19. We will see later on how it affects the
calculation.
2. Lateral MOSFETs have a poorly doped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD
clamping network shall thus be installed to
protect the MOSFET. In some low power
applications, a simple capacitor can also be used
since Vdrain max + V
in
) N(V
out
) V
f
)
) I
peak
L
f
C
tot
Ǹ
(eq. 15)
, where L
f
is the leakage
inductance, C
tot
the total capacitance at the drain
node (which is increased by the capacitor you
will wire between drain and source), N the Np:Ns
turn ratio, V
out
the output voltage, V
f
the
secondary diode forward drop and finally, I
peak
the maximum peak current. Worse case occurs
when the SMPS is very close to regulation, e.g.
the V
out
target is almost reached and I
peak
is still
pushed to the maximum. For this design, we have
selected our maximum voltage around 650 V (at
V
in
= 375 Vdc). This voltage is given by the RCD
clamp installed from the drain to the bulk
voltage. We will see how to calculate it later on.
3. Calculate the maximum operating duty−cycle for
this flyback converter operated in CCM:
d
max
+
NV
out
NV
out
) V
in,min
+
1
1 )
V
in,min
NV
out
+ 0.49
(eq. 16
)
4. To obtain the primary inductance, we have the
choice between two equations:
L +
(V
in
d)
2
f
SW
KP
in
(eq. 17)
, where K +
DI
L
I
1
and
defines the amount of ripple we want in CCM
(see Figure 43).
Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.

NCP1028P065G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
AC/DC Converters NCP1028 65 KHZ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet