REV. E
AD7701
–13–
Table III. Calibration Truth Table*
CAL SC1 SC2 Calibration Type Zero Reference FS Reference Sequence Calibration Time
00Self-Calibration AGND V
REF
One Step 3,145,655 Clock Cycles
11System Offset A
IN
First Step 1,052,599 Clock Cycles
01System Gain A
IN
Second Step 1,068,813 Clock Cycles
10System Offset A
IN
V
REF
One Step 2,117,389 Clock Cycles
*DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7701 has settled to the analog input. In all other
modes, DRDY falls as the device begins to settle.
between the multiplexer and the AD7701 is removed. Op amps
and other signal conditioning circuits may be used in front of
the AD7701 without worrying about their absolute gain or
offset errors. Note that the absolute value of the reference sup-
plied to the AD7701 is no longer important, provided it has
adequate short-term stability between calibration cycles, as full
scale is calibrated to the system reference.
If system offset errors are important but system gain errors are
not, then a one-step system calibration may be performed with
SC1 high and SC2 low. In this case, offset is calibrated against
A
IN
, which should be connected to system REF LO during
calibration, but full scale is calibrated against the AD7701’s
V
REF
input.
System calibration schemes will yield better accuracy than
self-calibration, even if there are no system errors. Using self-
calibration, errors arise due to the mismatch in source impedances
between the references during calibration (AGND and V
REF
)
and the analog input during normal operation. In system cali-
bration, the source impedances inherently remain identical such
that the theoretical limit to system accuracy is calibration reso-
lution. The practical limit is the noise floor of the AD7701.
Note that in system calibration, REF LO does not necessarily
mean the system ground or 0 V. The AD7701 can be calibrated
to measure between any two voltages that lie within its calibra-
tion range by deliberately making REF LO nonzero. For example,
if REF LO is 0.5 V and REF HI is 2.5 V, the unipolar span will
be between these limits.
CALIBRATION RANGE
When designing system calibration schemes, care must be taken
to ensure that the worst-case system errors do not cause the
overrange headroom of the AD7701 to be exceeded. Although
the measurement error caused by offset and gain errors can be
nulled out, the actual error voltages will still be present at the ana-
log input and can cause overloading of the analog modulator or
overflow of the digital filter. With a 2.5 V reference, the maxi-
mum input voltage is (+V
REF
+ 100 mV), and the minimum
input voltage is (–V
REF
– 100 mV).
POWER-UP AND CALIBRATION
A calibration cycle must be carried out after power-up to initial-
ize the device to a consistent starting condition and correct
calibration. The CAL pin must be held high for at least four
clock cycles, after which calibration is initiated on the falling
edge of CAL and takes a maximum of 3,145,655 clock cycles
(approximately 768 ms, with a 4.096 MHz clock). See Table III.
The type of calibration cycle initiated by CAL is determined by
the SC1 and SC2 inputs, in accordance with Table III.
The power dissipation and temperature drift of the AD7701 are
low, and no warm-up time is required before the initial calibra-
tion is performed. However, the system reference must have
stabilized before calibration is initiated.
POWER SUPPLY SEQUENCING
The positive digital supply (DV
DD
) must never exceed the posi-
tive analog supply (AV
DD
) by more than 0.3 V. Power supply
sequencing is, therefore, important. If separate analog and digi-
tal supplies are used, care must be taken to ensure that the
analog supply is powered up first.
It is also important that power is applied to the AD7701 before
signals at V
REF
, A
IN
, or the logic input pins in order to avoid any
possibility of latch-up. If separate supplies are used for the
AD7701 and the system digital circuitry, then the AD7701 should
be powered up first.
A typical scheme for powering the AD7701 from a single set of
±5 V rails is shown in Figure 7. In this circuit, AV
DD
and DV
DD
are brought along separate tracks from the same 5 V supply.
Thus, there is no possibility of the digital supply coming up
before the analog supply.
GROUNDING
The AD7701 uses the analog ground connection, AGND, as
the measurement reference node. It should be used as the refer-
ence node for both the analog input signal and the reference
voltage at the V
REF
pin.
The analog and digital power supplies to the AD7701 die are
pinned out separately to minimize coupling between the analog
and digital sections of the chip. All four supplies should be
decoupled separately to their respective grounds as shown in
Figure 7. The on-chip digital filtering of the AD7701 further
enhances power supply rejection by attenuating noise injected
into the conversion process.
SINGLE-SUPPLY OPERATION
Figure 17 shows a circuit to power the AD7701 from a single
10 V supply, using an op amp to provide a half supply refer-
ence point for AGND and DGND. As the digital I/O pins are
referenced to this point, level shifting is required for external
digital communications. If galvanic isolation is required in the
system, level shifting and isolation can both be provided by
opto-isolators.
