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AD7701ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
REV. E
AD7701
–3–
Parameter A, S Version
2
B, T Version
2
Unit Test Conditions/Comments
POWER REQUIREMENTS
8
Power Supply Voltages
Analog Positive Supply (AV
DD
) 4.5/5.5 4.5/5.5 V min/V max
Digital Positive Supply (DV
DD
) 4.5/AV
DD
4.5/AV
DD
V min/V max
Analog Negative Supply (AV
SS
) –4.5/–5.5 –4.5/–5.5 V min/V max
Digital Negative Supply (DV
SS
) –4.5/–5.5 –4.5/–5.5 V min/V max
Calibration Memory Retention
Power Supply Voltage 2.0 2.0 V min
DC Power Supply Currents
8
Analog Positive Supply (AI
DD
) 2.7 2.7 mA max Typically 2 mA
Digital Positive Supply (DI
DD
)2 2 mA max Typically 1 mA
Analog Negative Supply (AI
SS
) 2.7 2.7 mA max Typically 2 mA
Digital Negative Supply (DI
SS
) 0.1 0.1 mA max Typically 0.03 mA
Power Supply Rejection
9
Positive Supplies 70 70 dB typ
Negative Supplies 75 75 dB typ
Power Dissipation
Normal Operation 37 37 mW max SLEEP = Logic 1,
Typically 25 mW
Standby Operation
10
20 (40 S Version) 20 (40 T Version) µW max SLEEP = Logic 0,
Typically 10 µW
NOTES
1
The A
IN
pin presents a very high impedance dynamic load that varies with clock frequency.
2
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S, T Versions: –55°C to +125°C.
3
Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
4
Total drift over the specified temperature range since calibration at power-up at 25 °C. This is guaranteed by design and/or characterization. Recalibration at
any temperature will remove these errors.
5
In Unipolar mode, the offset can have a negative value (–V
REF
) such that the Unipolar mode can mimic Bipolar mode operation.
6
The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7
For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and
negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V
REF
+0.1).
8
All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9
Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10
CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
REV. E–4–
AD7701
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
DV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DV
DD
to AV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Analog Input
Voltage to AGND . . . . . . . . AV
SS
– 0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . ±10 mA
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial CERDIP (A, B Versions) . . . . . . –40°C to +85°C
Extended CERDIP (S, T Versions) . . . . . –55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
PDIP, CERDIP, SOIC
MODE
SC1
DGND
CLKOUT
CLKIN
AGND
DV
SS
AV
SS
A
IN
V
REF
SDATA
SCLK
SC2
CAL
AV
DD
DV
DD
DRDY
CS
BP/UP
SLEEP
TOP VIEW
(Not to Scale)
AD7701
1
2
3
4
5
6
7
8
9
10
14
13
12
11
20
19
18
17
16
15
SSOP
MODE
SC1
DGND
CLKOUT
CLKIN
AGND
DV
SS
AV
SS
A
IN
V
REF
SDATA
SCLK
SC2
CAL
AV
DD
DV
DD
DRDY
CS
BP/UP
SLEEP
TOP VIEW
(Not to Scale)
AD7701
1
2
3
4
5
6
7
8
9
10
14
13
12
11
20
19
18
17
16
15
21
22
23
24
25
26
27
28
NC
NC
NC
NC
NC
NC
NC
NC
NC = NO CONNECT
PIN CONFIGURATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7701 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature Linearity Package
Model Range Error (% FSR) Options*
AD7701AN –40°C to +85°C 0.003 N-20
AD7701BN –40°C to +85°C 0.0015 N-20
AD7701AR –40°C to +85°C 0.003 R-20
AD7701BR –40°C to +85°C 0.0015 R-20
AD7701ARS –40°C to +85°C 0.003 RS-28
AD7701AQ –40°C to +85°C 0.003 Q-20
AD7701BQ –40°C to +85°C 0.0015 Q-20
AD7701SQ –55°C to +125°C 0.003 Q-20
AD7701TQ –55°C to +125°C 0.0015 Q-20
*N = PDIP; Q = CERDIP; R = SOIC; RS = SSOP.
REV. E
AD7701
–5–
PIN FUNCTION DESCRIPTIONS
Pin No.
PDIP,
CERDIP,
SOIC SSOP Mnemonic Description
11 MODE Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in
the Asynchronous Communications (AC) mode. The SCLK pin is configured as an
input, and data is transmitted in two bytes, each with one start bit and two stop bits. If
MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected.
SCLK is configured as an input, and the output appears without formatting, the MSB
coming first. If MODE is tied to +5 V, the AD7701 operates in the Synchronous
Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency of
f
CLKlN
/4 and 25% duty cycle.
22 CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between
CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected.
33 CLKIN Clock Input for External Clock.
4, 17 4, 25 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines
the type of calibration performed.
55 DGND Digital Ground. Ground reference for all digital signals.
68 DV
SS
Digital Negative Supply, –5 V Nominal.
6, 7, 9, 11, NC No Connect.
18, 21, 22, 23
710 AV
SS
Analog Negative Supply, –5 V Nominal.
812 AGND Analog Ground. Ground reference for all analog signals.
913 A
IN
Analog Input.
10 14 V
REF
Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale
in the Unipolar mode and of both positive and negative full scale in Bipolar mode.
11 15 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7701 goes into a low power mode
with typically 10 µW power consumption.
12 16 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a uni-
polar input range going from AGND to V
REF
. When Pin 12 is high, the AD7701 is
configured for a bipolar input range, ±V
REF
.
13 17 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7701
is reset and performs a calibration cycle when CAL is brought low again. The CAL pin
can also be used as a strobe to synchronize the operation of several AD7701s.
14 19 AV
DD
Analog Positive Supply, +5 V Nominal.
15 20 DV
DD
Digital Positive Supply, +5 V Nominal.
16 24 CS Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial
data in a format determined by the state of the MODE pin.
18 26 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It
goes high after transmission of a word is completed. It also goes high for four clock
cycles when a new data-word is being loaded into the output register, to indicate that
valid data is not available, irrespective of whether data transmission is complete or not.
19 27 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, depen-
dent on the type of serial data transmission that has been selected by the MODE pin.
When configured as an output in the Synchronous Self-Clocking mode, it has a fre-
quency of f
CLKIN
/4 and a duty cycle of 25%.
20 28 SDATA Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial
word. The transmission format is determined by the state of the MODE pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7701ARZ

Mfr. #:
Buy AD7701ARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit IC
Lifecycle:
New from this manufacturer.
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