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AD7701ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
REV. E–6–
AD7701
TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V 10%; AV
SS
= DV
SS
= –5 V 10%; AGND = DGND = O V; f
CLKIN
=
4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
DD
; unless otherwise noted.)
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments
f
CLKIN
3, 4
200 200 kHz min Master Clock Frequency: Internal Gate Oscillator.
55 MHz max Typically 4.096 MHz.
200 200 kHz min Master Clock Frequency: Externally Supplied.
55 MHz max
t
r
5
50 50 ns max Digital Output Rise Time. Typically 20 ns.
t
f
5
50 50 ns max Digital Output Fall Time. Typically 20 ns.
t
1
00 ns min SC1, SC2 to CAL High Setup Time.
t
2
50 50 ns min SC1, SC2 Hold Time after CAL Goes High.
t
3
6
1000 1000 ns min SLEEP High to CLKIN High Setup Time.
SSC MODE
t
4
7
3/f
CLKIN
3/f
CLKIN
ns max Data Access Time (CS Low to Data Valid).
t
5
100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ).
t
6
250 250 ns min MSB Data Setup Time. Typically 380 ns.
t
7
300 300 ns max SCLK High Pulsewidth. Typically 240 ns.
t
8
790 790 ns max SCLK Low Pulsewidth. Typically 730 ns.
t
9
8
l/f
CLKIN
+200 l/f
CLKIN
+200 ns max SCLK Rising Edge to Hi-Z Delay (l/f
CLKIN
+ 100 ns typ).
t
10
8, 9
(4/f
CLKIN
) +200 (4/f
CLKIN
) +200 ns max CS High to Hi-Z Delay.
SEC MODE
f
SCLK
55 MHz Serial Clock Input Frequency.
t
11
35 35 ns min SCLK Input High Pulsewidth.
t
12
160 160 ns min SCLK Low Pulsewidth.
t
13
7, 10
160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns.
t
14
11
150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
t
15
8
250 250 ns max CS High to Hi-Z Delay.
t
16
8
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
AC MODE
t
17
40 40 ns min CS Setup Time. Typically 20 ns.
t
18
180 180 ns max Data Delay Time. Typically 90 ns.
t
19
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7701 is production tested with f
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
In order to synchronize several AD7701s together using the SLEEP pin, this specification must be met.
7
t
4
and t
13
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t
9
, t
10
, t
15
, and t
16
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9
If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
REV. E
AD7701
–7–
1.6mA
200µA
C
L
100pF
TO
OUTPUT
PIN
I
OH
2.1V
+
I
OL
Figure 1. Load Circuit for Access
Time and Bus Relinquish Time
DATA
VA LI D
t
10
HI-Z
SDATA
CS
Figure 3. SSC Mode Data
Hold Time
CAL
SC1, SC2
SC1, SC2 VALID
t
1
t
2
Figure 2a. Calibration Control Timing
DATA
VA LI D
t
15
HI-Z
SDATA
CS
Figure 4a. SEC Mode Data Hold Time
CLKIN
SLEEP
t
3
Figure 2b.
SLEEP
Mode Timing
HI-Z
DB15 DB14
DB1
DB0
HI-Z
SDATA
DRDY
CS
t
12
t
11
t
13
t
14
SCLK
t
16
Figure 4b. SEC Mode Timing Diagram
HI-Z
DB15 DB14
DB1 DB0
HI-Z
SCLK
SDATA
CLKIN
CS
HI-Z
t
7
t
6
t
5
t
4
t
8
t
5
Figure 5. SSC Mode Timing Diagram
HI-Z
START
DB8
DB9
DB7
STOP 1
STOP 2
HI-Z
HIGH BYTE
LOW BYTE
SDATA
SCLK
DRDY
CS
t
17
t
18
t
19
Figure 6. AC Mode Timing Diagram
DEFINITION OF TERMS
Linearity Error
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first
code transition (000 . . . 000 to 000 . . . 001) and full scale, a
point 1.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). The error is expressed as a percentage of full scale.
Differential Linearity Error
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSBs. A differential linearity specification of ± 1 LSB or less
guarantees monotonicity.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (V
REF
±3/2 LSBs).
It applies to both positive and negative analog input ranges and
is expressed in microvolts.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the Uni-
polar mode. It is expressed in microvolts.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating
in the Bipolar mode. It is expressed in microvolts.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
(–V
REF
+ 0.5 LSB) when operating in the Bipolar mode. It is
expressed in microvolts.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +V
REF
(for example, noise
peaks or excess voltages due to system gain errors in system
calibration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter. It is
expressed in millivolts.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages below
–V
REF
without overloading the analog modulator or overflowing
the digital filter. Note that the analog input will accept negative
voltage peaks even in the Unipolar mode. The overhead is
expressed in millivolts.
REV. E–8–
AD7701
Offset Calibration Range
In the system calibration modes (SC2 low), the AD7701 cali-
brates its offset with respect to the A
IN
pin. The offset calibration
range specification defines the range of voltages, expressed as a
percentage of V
REF
, that the AD7701 can accept and still accu-
rately calibrate offset.
Full-Scale Calibration Range
This is the range of voltages that the AD7701 can accept in the
system calibration mode and still correctly calibrate full scale.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7701’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7701 can
accept and still accurately calibrate gain. The input span is
expressed as a percentage of V
REF.
GENERAL DESCRIPTION
The AD7701 is a 16-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical, or biological processes. It contains a charge-balancing
(sigma-delta) ADC, calibration microcontroller with on-chip
static RAM, clock oscillator, and serial communications port.
The analog input signal to the AD7701 is continuously sampled
at a rate determined by the frequency of the master clock, CLKIN.
A charge-balancing A/D converter (sigma-delta modulator)
converts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. A six-pole Gaussian digi-
tal low-pass filter processes the output of the modulator and
updates the 16-bit output register at a 4 kHz rate. The output
data can be read from the serial port randomly or periodically at
any rate up to 4 kHz.
AD7701
MODE
SDATA
DGND
CLKOUT
CLKIN
AGND
SCLK
SC2
CAL
CS
BP/UP
DV
SS
DV
DD
SLEEP
RANGE
SELECT
CALIBRATE
ANALOG
INPUT
ANALOG
GROUND
–5V
ANALOG
SUPPLY
0.1µF
+5V
ANALOG
SUPPLY
2.5V
0.1µF
0.1µF
VOLTAG E
REFERENCE
DRDY
0.1µF
10µF
AV
DD
V
REF
A
IN
AV
SS
0.1µF
10µF
READ
READY
READ
(TRANSMIT)
SERIAL
CLOCK
SERIAL
DATA
Figure 7. Typical System Connection Diagram
The AD7701 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
Other system components may also be included in the calibra-
tion loop to remove offset and gain errors in the input channel.
For battery operation, the AD7701 also offers a standby mode
that reduces idle power consumption to typically 10 µW.
THEORY OF OPERATION
The general block diagram of a sigma-delta ADC is shown in
Figure 8. It contains the following elements:
1. A sample-hold amplifier
2. A differential amplifier or subtracter
3. An analog low-pass filter
4. A 1-bit A/D converter (comparator)
5. A 1-bit DAC
6. A digital low-pass filter
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
ANALOG
LOW-PASS
FILTER
COMPARATOR
DIGITAL DATA
S/H AMP
DAC
DIGITAL
FILTER
Figure 8. General Sigma-Delta ADC
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
SNR = (6.02 × number of bits + 1.76) dB
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7701 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 kHz to 8 kHz. Since the specified
analog input bandwidth of the AD7701 is only 0 Hz to 10 Hz,
the noise energy in this bandwidth would be only 1/800 of the
total quantization noise, even if the noise energy were spread
evenly throughout the spectrum. It is reduced still further by
analog filtering in the modulator loop, which shapes the quanti-
zation noise spectrum to move most of the noise energy to
frequencies above 10 Hz. The SNR performance in the 0 Hz to
10 Hz range is conditioned to the 16-bit level in this fashion.
The output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
that minimizes the difference signal. The digital data that repre-
sents the analog input voltage is in the duty cycle of the pulse
train appearing at the output of the comparator. It can be
retrieved as a parallel binary data-word using a digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first-order, sigma-
delta ADC is shown in Figure 9. This contains only a first-order,
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: charge-balancing ADCs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7701ARZ

Mfr. #:
Buy AD7701ARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit IC
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