LTC2875
16
2875f
For more information www.linear.com/LTC2875
applicaTions inForMaTion
SPLIT Pin Output for Split Termination Support
Split termination is an optional termination technique
to reduce common mode voltage perturbations that
can produce EME. A split terminator divides the single
line-end termination resistor (nominally 120Ω) into two
series resistors of half the value of the single termination
resistor (Figure 2). The center point of the two resistors
is connected to a low impedance voltage source that sets
the recessive common mode voltage.
Split termination suppresses common mode voltage
perturbations by providing a low impedance load to com
-
mon mode noise sources such as transmitter noise or
coupling
to external noise sources. In the case of single
resistor termination, the only load on a common mode
noise source is the parallel impedance of the input resis-
tors of the CAN transceivers on the bus. This results in a
common mode impedance of several kilohms for a small
network. The split termination, on the other hand, provides
a common mode load equal to the parallel resistance of
the two split termination resistors, or ¼ the resistance of
the single termination resistor (30Ω). This low common
mode impedance results in a reduction of the common
mode noise voltage compared to the much higher com-
mon mode impedance of the single resistor termination.
The SPLIT pin on the LTC2875 provides a buffered voltage
to bias the mid-point of the split termination resistors. The
voltage on the SPLIT pin matches the common mode volt-
age established by the transmitter in the dominant state
and the receiver input resistor bias during the recessive
state: V
CC
/2 when V
CC
= 5V and V
CC
/2+0.3V when V
CC
=
3.3V. Decouple SPLIT with a 4.7nF capacitor to ground
to lower the AC impedance to better suppress fast tran-
sients. SPLIT is a high voltage fault tolerant output that
tolerates the same ±60V overvoltage faults and ±25kV
ESD discharges as CANH and CANL.
One disadvantage of the SPLIT termination is higher power
supply current if the two terminating transceivers differ in
their common mode voltage due to differences in V
CC
or
GND potential or to chip to chip variations in the internal
reference voltages. This will result in the transceiver with
the higher common mode voltage sourcing current into
the bus lines through its SPLIT pin, while the transceiver
with the lower common mode voltage will sink current
through its SPLIT pin.
Ideal Passive Behavior to CAN Bus With Supply Off
When
the power supply is removed or the chip is in shut-
down, the CANH and CANL pins are in a high impedance
state.
The receiver inputs are isolated from the CANH and
CANL nodes by FET switches which opens in the absence
of power, thereby preventing the resistor dividers on the
receiver input from loading the bus. The high impedance
state of the receiver is maintained over a range determined
by the ESD protection of the receiver input, typically −0.3V
to 10V. For bus voltages outside this range, the current
flowing into the receiver is governed by the conduction
voltages of the ESD device and the 40k nominal receiver
input resistance.
Micropower Shutdown Mode
The low power shutdown mode is entered by raising the
voltage on the RS pin above its V
IH_RS
threshold. This turns
off all circuits that draw DC bias currents and disables all
chip functionality. Any remaining supply current in shut
-
down is due to semiconductor device leakage currents. All
the outputs —CANH, CANL, SPLIT, and RXD— are in the
high impedance state, with RXD pulled up to V
CC
through a
500kΩ resistor to ensure it remains in the recessive state.
The chip
is enabled by bringing the RS pin below its V
IL_RS
threshold. The RXD output goes active after the time
delay t
ENRX
(40µs max) and the SPLIT pin goes active at
approximately the same time. CANH and CANL switch to
the dominant state at the first high-to-low transition of
TXD after the t
ENTX
delay.
Auxiliary Protection for IEC Surge, EFT and ESD
A transceiver used in an industrial setting may be exposed
to extremely high levels of electrical overstress due to
phenomena such as lightning surge, electrical fast tran
-
sient (EFT) from
switching high current inductive loads,
and electrostatic discharge (ESD) from the discharge of
electrically charged personnel or equipment. Test methods
to evaluate immunity of electronic equipment to these
phenomena are defined in the IEC standards 61000-4-2,
