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854104AGLF

P1-P3P4-P6P7-P9P10-P12P13-P15
DATASHEET
Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
ICS854104
ICS854104AG REVISION A JANUARY 30, 2014 1 ©2014 Integrated Device Technology, Inc.
General Description
The ICS854104 is a low skew, high performance 1-to-4
Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS), the ICS854104 provides a low power,
low noise, solution for distributing clock signals over controlled
impedances of 100. The ICS854104 accepts a differential input
level and translates it to LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
ICS854104 ideal for those applications demanding well defined
performance and repeatability.
Features
• Four differential LVDS output pairs
• One differential clock input pair
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Each output has an individual OE control
• Maximum output frequency: 700MHz
• Translates differential input signals to LVDS levels
• Additive phase jitter, RMS: 0.232ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.3ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram Pin Assignment
ICS854104
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
CLK
OE2
OE3
OE1
OE0
nCLK
Pulldown
Pullup/Pulldown
Pullup
Pullup
Pullup
Pullup
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
OE3
nCLK
CLK
GND
V
DD
OE2
OE1
OE0
ICS854104AG REVISION A JANUARY 30, 2014 2 ©2014 Integrated Device Technology, Inc.
ICS854104 DATASHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Output Enable Function Table
Number Name Type Description
1 OE0 Input Pullup
Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
2 OE1 Input Pullup
Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
3 OE2 Input Pullup
Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
4V
DD
Power Positive supply pin.
5 GND Power Power supply ground.
6 CLK Input Pulldown Non-inverting differential clock input.
7 nCLK Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
8 OE3 Input Pullup
Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
9, 10 nQ3, Q3 Output Differential output pair. LVDS interface levels.
11, 12 nQ2, Q2 Output Differential output pair. LVDS interface levels.
13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels.
15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
Inputs Outputs
OE[3:0] Q[0:3], nQ[0:3]
0 High-Impedance
1 Active (default)
ICS854104AG REVISION A JANUARY 30, 2014 3 ©2014 Integrated Device Technology, Inc.
ICS854104 DATASHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4C. Differential DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance,
JA
100.3°C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 75 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input Low Current V
DD
= 3.465V, V
IN
= 0V -150 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High
Current
CLK, nCLK V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low
Current
CLK V
DD
= 3.465V, V
IN
= 0V -5 µA
nCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage;
NOTE 1
0.15 1.3 V
V
CMR
Common Mode Input
Voltage; NOTE 1, 2
GND + 0.5 V
DD
– 0.85 V
P1-P3P4-P6P7-P9P10-P12P13-P15

854104AGLF

Mfr. #:
Buy 854104AGLF
Manufacturer:
IDT
Description:
Clock Buffer 4 LVDS OUTPUT BUFFER
Lifecycle:
New from this manufacturer.
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