OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

854104AGLF

P1-P3P4-P6P7-P9P10-P12P13-P15
ICS854104AG REVISION A JANUARY 30, 2014 7 ©2014 Integrated Device Technology, Inc.
ICS854104 DATASHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
Output Rise/Fall Time
Differential Output Voltage Setup
Offset Voltage Setup
20%
80%
80%
20%
t
R
t
F
V
OD
Q[0:3]
nQ[0:3]
ICS854104AG REVISION A JANUARY 30, 2014 8 ©2014 Integrated Device Technology, Inc.
ICS854104 DATASHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
V_REF
Single Ended Clock Input
V
DD
CLK
nCLK
R1
1K
C1
0.1u R2
1K
ICS854104AG REVISION A JANUARY 30, 2014 9 ©2014 Integrated Device Technology, Inc.
ICS854104 DATASHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the V
PP
and V
CMR
input requirements. Figures 2A to 2F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2A. CLK/nCLK Input Driven by an IDT Open
Emitter LVHSTL Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
CSL
*R
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60Ω
2.5V
3.3V
R1
120Ω
R2
120Ω
R3
120
Ω
R4
120
Ω
P1-P3P4-P6P7-P9P10-P12P13-P15

854104AGLF

Mfr. #:
Buy 854104AGLF
Manufacturer:
IDT
Description:
Clock Buffer 4 LVDS OUTPUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet