NB3H73113G00MNR2G Datasheet NB3H73113G00MNR2G | P1-P3

March, 2017 − Rev. 0

1 Publication Order Number:

NB3H73113G/D

NB3H73113G

3.3 V / 2.5 V Programmable

OmniClock Generator with

C / SMBus Interface

The NB3H73113G, which is a member of the OmniClock family, is

a one−time programmable (OTP), low power PLL−based clock

generator that supports any output frequency from 8 kHz to 200 MHz.

The device accepts fundamental mode parallel resonant crystal or a

single ended (LVCMOS/LVTTL) reference clock as input. It

generates either three single ended (LVCMOS/LVTTL) outputs, or

one single ended output and one differential

(LVPECL/LVDS/HCSL/CML) output. The output signals can be

modulated using the spread spectrum feature of the PLL

(programmable spread spectrum type, deviation and rate) for

applications demanding low electromagnetic interference (EMI).

Individual output enable pins OE[2:0] are available to enable/disable

the outputs. Individual output voltage pins VDDO[2:0] are available

to independently set the output voltage of each output. The device

supports SMBus / I

C interface with SCLK and SDATA signals. Using

the standard protocol, data in the device registers can be modified to

support different configurations. Using the PLL bypass mode, it is

possible to get a copy of the input clock on any or all of the outputs.

The device can be powered down using the Power Down pin (PD#). It

is possible to program the internal input crystal load capacitance and

the output drive current provided by the device. The device also has

automatic gain control (crystal power limiting) circuitry which avoids

the device overdriving the external crystal.

Features

• Member of the OmniClock Family of Programmable

Clock Generators

• Operating Power Supply: 3.3 V ±10%, 2.5 V ±10%

• Supports SMBus / I

C Interface

• I/O Standards

♦ Inputs: LVCMOS/LVTTL, Fundamental Mode

Crystal

♦ Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL

♦ Outputs: LVPECL, LVDS, HCSL and CML

• 3 Programmable Single Ended (LVCMOS/LVTTL)

Outputs from 8 kHz to 200 MHz

• 1 Programmable Differential Clock Output up to

200 MHz

• Input Frequency Range

♦ Crystal: 3 MHz to 50 MHz

♦ Reference Clock: 3 MHz to 200 MHz

• Configurable Spread Spectrum Frequency Modulation

Parameters (Type, Deviation, Rate)

• Individual Output Enable Pins

• Independent Output Voltage Pins

• Programmable Internal Crystal Load Capacitors

• Programmable Output Drive Current for Single Ended

Outputs

• Power Saving Mode through Power Down Pin

• Programmable PLL Bypass Mode

• Programmable Output Inversion

• Programming and Evaluation Kit Available for Field

Programming and Quick Evaluation

• Temperature Range −40°C to 85°C

• Packaged in 16−pin QFN

• These are Pb−Free Devices

Typical Applications

• eBooks and Media Players

• Smart Wearables, Smart Phones, Portable Medical and

Industrial Equipment

• Set Top Boxes, Printers, Digital Cameras and

Camcorders

www.onsemi.com

QFN16

CASE 485AE

MARKING DIAGRAM

See detailed ordering and shipping information on page 23 o

this data sheet.

ORDERING INFORMATION

3H73113G = Specific Device Code

xx = Specific Program Code (Default

‘00’ for Unprogrammed Part)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

3H731

13Gxx

ALYWG

(Note: Microdot may be in either location)

NB3H73113G

www.onsemi.com

BLOCK DIAGRAM

Figure 1. Simplified Block Diagram

Phase

Detector

Charge

Pump

VCO

CMOS/

DIFF

buffer

CMOS/

DIFF

buffer

CMOS

buffer

Feedback

Divider

XIN/ CLKIN

XOUT

Crystal

CLK0

VDD

GND

Output

Divider

Output

Divider

Output

Divider

PLL Block

VDDO0

CLK1

VDDO1

CLK2

VDDO2

PLL Bypass Mode

Clock Buffer/

Crystal

Oscillator And

AGC

SDATASCLK

Configuration

Memory

Frequency

and SS

Output control

PD#

Input

Decoder

Crystal/Clock Control

OE0

OE1

OE2

GNDO

Notes:

1. CLK0 and CLK1 can be configured to be one LVPECL, LVDS, HCSL or CML output, or two single ended LVCMOS/LVTTL outputs.

2. Dotted lines are the programmable control signals to internal IC blocks.

3. OE[2:0], SCLK and SDATA have internal pull up resistors. PD# has internal pull down resistor.

PIN FUNCTION DESCRIPTION

Figure 2. Pin Connections (Top View) − QFN16 (with EPAD)

VDD

VDDO1

CLK1

CLK0

SCLK

SDATA

VDDO2

CLK2

XIN/CLKIN

XOUT

PD#

GND

OE0

OE1

OE2

VDDO0

GNDO

(EPAD)

NB3H73113G

8765

13141516

NB3H73113G

www.onsemi.com

Table 1. PIN DESCRIPTION

Pin No. Pin Name Pin Type Description

1 XIN/CLKIN Input 3 MHz to 50 MHz crystal input connection or an external single ended reference

input clock between 3 MHz and 200 MHz.

2 XOUT Output Crystal output. Float this pin when external reference clock is connected at XIN.

3 PD# Input Asynchronous LVCMOS/LVTTL input. Active Low Master Reset to disable the

device and set outputs Low. Internal pull−down resistor. This pin needs to be pulled

High for normal operation of the chip.

4 GND Ground Power supply ground.

5, 6, 7 OE[2:0] Input 2−Level LVCMOS/LVTTL Inputs for Enabling/Disabling output clocks CLK[2:0]

respectively. Internal pull−up resistor.

8 VDDO0 Power CLK0 Output power supply ≤ VDD

9 CLK0 SE/DIFF Output Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also

be a copy of the input clock. The single ended output will be LOW and differential

outputs will be complementary LOW/HIGH until the PLL has locked and the

frequency has stabilized.

10 CLK1 SE/DIFF Output Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also

be a copy of the input clock. The single ended output will be LOW and differential

outputs will be complementary LOW/HIGH until the PLL has locked and the

frequency has stabilized.

11 VDDO1 Power CLK1 Output power supply ≤ VDD

12 VDD Power 3.3V / 2.5V power supply.

13 CLK2 SE Output Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals. Using PLL

Bypass mode, the output can also be a copy of the input clock. The single ended

output will be LOW until the PLL has locked and the frequency has stabilized.

14 VDDO2 Power CLK2 Output power supply ≤ VDD

15 SDATA Input / Output I

C / SMBus Interface Signal SDATA

16 SCLK Input I

C / SMBus Interface Signal SCLK

EPAD GNDO Ground Power supply ground for Outputs.

Table 2. POWER DOWN FUNCTION TABLE

PD# Function

0 Device Powered Down

1 Device Powered Up

Table 3. OUTPUT ENABLE FUNCTION TABLE

OE[2:0] Function

0 CLK Disabled

1 CLK Enabled

TYPICAL CRYSTAL PARAMETERS

Crystal: Fundamental Mode Parallel Resonant

Frequency: 3 MHz to 50 MHz

Table 4. MAX CRYSTAL LOAD CAPACITORS

RECOMMENDATION

Crystal Frequency Range Max Cap Value

3 MHz − 30 MHz 20 pF

30 MHz − 50 MHz 10 pF

Shunt Capacitance (C0): 7 pF (Max)

Equivalent Series Resistance 150 W (Max)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

NB3H73113G00MNR2G

Mfr. #:

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Manufacturer:

ON Semiconductor

Description:

Clock Generators & Support Products PLL CLOCK GENERATOR

Lifecycle:

New from this manufacturer.

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NB3H73113G00MNR2G