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NB3H73113G00MNR2G

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NB3H73113G
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19
Figure 17. Simplified LVCMOS Output Structure
VDD
Drive Strength
selection
CLKx
Drive Strength
selection
LVDS Interface
Differential signaling like LVDS has inherent advantage
of common mode noise rejection and low noise emission,
and thus a popular choice for clock distribution in systems.
TIA/EIA−644 or LVDS is a standard differential,
point−to−point bus topology that supports fast switching
speeds and has the benefit of low power consumption. The
driver consists of a low swing differential with constant
current of 3.5 mA through the differential pair, and
generates switching output voltage across a 100 W
terminating resistor (externally connected or internal to the
receiver). Power dissipation in LVDS standard ((3.5 mA)
2
x
100 W = 1.2 mW) is thus much lower than other differential
signalling standards.
A fan−out LVDS buffer (like ON Semiconductor’s
NB6N1xS and NB6L1xS) can be used as an extension to
provide clock signal to multiple LVDS receivers to drive
multiple point−to−point links to receiving node.
VDDO
Vin
+
_
CLK 1
CLK 0
RT
100 W
+
_
Vout
Iss
Iss
Figure 18. Simplified LVDS Output Structure with Termination
NB3H73113G
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20
LVPECL Interface
The LVPECL driver is designed to drive a 50 W
transmission line from a constant current differential and a
low impedance emitter follower. On the NB3H73113G, this
differential standard is supported for VDDO supply voltage
of 2.5 V and above. In the system, the clock receiver must
be referenced at the same supply voltage as VDDO for
reliable functionality. The termination to receiver V
CC
− 2 V
(1.3 V for a 3.3 V VDDO supply, and 0.5 V for a 2.5 V
VDDO supply) used in evaluation boards, is rarely used in
system boards as it adds another power supply on the system
board. Thus, Thevenin’s equivalent circuit (Figure 20) for
this termination or a Y−type termination (Figure 21) is often
used in systems. Termination techniques for LVPECL are
detailed in the application note “Termination of ECL
Devices with EF (Emitter Follower) OUTPUT Structure −
AND8020”.
VDDO
Isc
CLK1
CLK0
VCC - 2V
50 W
50 W
Figure 19. Simplified LVPECL Output Structure with Termination
NB3H73113G
CLK1
R2
CLK0
VCC
R2
R1
R1
VDDO
Figure 20. LVPECL Thevenin Termination
NB3H73113G
CLK1
50 W
CLK0
50 W
RT
VDDO
Figure 21. LVPECL Y−Termaination
System Supply
Practical R2
(W)
Practical R1 (W)
2.5 V System 62(5%) 240(5%)
3.3 V system 82(5%) 130(5%)
Y−Termination
RT (W)
2.5 V System 50
3.3 V system 18
The termination should be placed as close to the receiver
as possible to avoid unterminated stubs that can cause signal
integrity issues.
CML Interface
A CML driver consists of an NMOS open drain constant
current differential driving 16 mA current into a 50 W load
terminated to the supply voltage at the receiver. This
termination resistor can be external or internal to the
receiver and needs to be as close as possible to the receiver.
On the NB3H73113G, this differential standard is supported
for VDDO supply voltage 2.5 V and above. The termination
techniques used for a CML driver are detailed in application
note “Termination and Interface of ON Semiconductor ECL
Devices With CML (Current Mode Logic) OUTPUT
Structure − AND8173”
NB3H73113G
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21
Isc = 16mA
CLK 1
CLK 0
VCC (receiver )
50 W50 W
Figure 22. Simplified CML Output Structure with Termination
HCSL Termination
HCSL is a differential signaling standard commonly used
in PCIe systems. The HCSL driver is typical 14.5 mA
switched current open source output that needs a 50 W
termination resistor to ground near the source, and generates
725 mV of signal swing. A series resistor (10 W to 33 W) is
optionally used to achieve impedance matching by limiting
overshoot and ringing due to the rapid rise of current from
the output driver. The open source driver has high internal
impedance; thus a series resistor up to 33 W does not affect
the signal integrity. This resistor can be avoided for low
VDDO supply (1.8 V) of operation, unless impedance
matching requires it.
CLK1
CLK0
2.6mA
14.5mA
50 W 50 W
Figure 23. Simplified HCSL Output Structure with Termination
Field Programming Kit and Software
The NB3H73113G can be programmed by the user using
the ‘Clock Cruiser Programmable Clock Kit’. This device
uses the 16L daughter card on the hardware kit. To design a
new clock, ‘Clock Cruiser Software’ is required to be
installed from the ON Semiconductor website. The user
manuals for the hardware kit Clock Cruiser Programmable
Clock Kit and Clock Cruiser Software can be found
following this link www.onsemi.com
.
Recommendation for Clock Performance
Clock performance is specified in terms of Jitter in the
time domain. Details and measurement techniques of
Cycle−cycle jitter, period jitter, TIE jitter and Phase Noise
are explained in application note AND8459/D.
In order to have a good clock signal integrity for minimum
data errors, it is necessary to reduce the signal reflections.
The reflection coefficient can be zero only when the source
impedance equals the load impedance. Reflections are based
on signal transition time (slew rate) and due to impedance
mismatch. Impedance matching with proper termination is
required to reduce the signal reflections. The amplitude of
overshoots is due to the difference in impedance and can be
minimized by adding a series resistor (Rs) near the output
pin. Greater the difference in impedance, greater is the
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NB3H73113G00MNR2G

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Buy NB3H73113G00MNR2G
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products PLL CLOCK GENERATOR
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