17
LTC3832/LTC3832-1
sn3832 3832fs
APPLICATIO S I FOR ATIO
WUUU
between the top of the resistor divider network and the V
FB
pin to create a pole-zero pair in the loop compensation.
The zero location is prior to the pole location and thus,
phase lead can be added to boost the phase margin at the
loop crossover frequency. The pole and zero locations are
located at:
f
ZC2
= 1/[2π(R2)(C2)] and
f
PC2
= 1/[2π(R1||R2)(C2)]
where R1||R2 is the parallel combination resistance of R1
and R2. For low R2/R1 ratios there is not much separa-
tion between f
CZ2
and f
PC2
. In this case, use multiple
capacitors with a high ESR • capacitance product to bring
f
ESR
close to f
CO
. Choose C2 so that the zero is located at
a lower frequency compared to f
CO
and the pole location
is high enough that the closed loop has enough phase
margin for stability. Figure 10c shows the Bode plot using
phase lead compensation around the LTC3832 resistor
divider network.
Although a mathematical approach to frequency compen-
sation can be used, the added complication of input and/or
output filters, unknown capacitor ESR, and gross operat-
ing point changes with input voltage, load current varia-
tions, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.
Table 2 shows the suggested compensation component
value for 3.3V to 2.5V applications based on Sanyo OS-CON
4SP820M low ESR output capacitors.
Table 2. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 820µF Sanyo OS-CON
4SP820M Output Capacitors
L1 (µH) C
OUT
(µF) R
C
(kΩ)C
C
(nF) C1 (pF) C2 (pF)
1.2 1640 9.1 4.7 560 1500
1.2 2460 15 4.7 330 1500
1.2 4100 24 3.3 270 1500
2.4 1640 22 4.7 330 1500
2.4 2460 33 3.3 220 1500
2.4 4100 43 2.2 180 1500
4.7 1640 33 3.3 120 1500
4.7 2460 56 2.2 100 1500
4.7 4100 91 2.2 100 1500
Table 3 shows the suggested compensation component
values for 3.3V to 2.5V applications based on 470µF Sanyo
POSCAP 4TPB470M output capacitors.
Table 3. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 470µF Sanyo POSCAP
4TPB470M Output Capacitors
L1 (µH) C
OUT
(µF) R
C
(kΩ)C
C
(µF) C1 (pF)
1.2 1410 13 0.0047 100
1.2 2820 27 0.0018 56
1.2 4700 51 0.0015 47
2.4 1410 33 0.0033 56
2.4 2820 62 0.0022 15
2.4 4700 82 0.001 39
4.7 1410 62 0.0022 15
4.7 2820 150 0.0015 10
4.7 4700 220 0.0015 2
Table 4 shows the suggested compensation component
values for 3.3V to 2.5V applications based on 1500µF
Sanyo MV-WX output capacitors.
Table 4. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 1500µF Sanyo MV-WX
Output Capacitors
L1 (µH) C
OUT
(µF) R
C
(kΩ)C
C
(µF) C1 (pF)
1.2 4500 39 0.0042 180
1.2 6000 56 0.0033 120
1.2 9000 82 0.0033 100
2.4 4500 82 0.0033 82
2.4 6000 100 0.0022 56
2.4 9000 150 0.0022 68
4.7 4500 120 0.0022 39
4.7 6000 220 0.0022 27
4.7 9000 220 0.0015 33
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3832.
These items are also illustrated graphically in the layout
diagram of Figure 11. The thicker lines show the high
current paths. Note that at 10A current levels or above,
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 10A.
