ADLD8403ACPZ-R2

Data Sheet ADLD8403
Rev. D | Page 3 of 10
SPECIFICATIONS
V
CC
= 12.5 V, R
L
= 100 Ω, G
DIFF
= 13 (fixed), PD_A = 0, PD_B = 0, T = 25°C, typical DSL application circuit, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
−3 dB Small Signal Bandwidth 8 MHz V
OUT
= 0.1 V p-p, differential
3 dB Large Signal Bandwidth 8 MHz V
OUT
= 2 V p-p, differential
Differential Gain 12.8 13 13.2 V/V
NOISE/DISTORTION PERFORMANCE
Multitone Power Ratio (MTPR) −65 dBc 26 kHz to 2.2 MHz, Z
LINE
= 100 Ω, differential load
Differential Output Noise 120 nV/√Hz f = 10 kHz
INPUT CHARACTERISTICS
Referred to Output (RTO) Offset Voltage <100 mV Single-ended
15 200 mV Differential
Input Resistance 8 kΩ Differential
1
pF
Differential
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing 43.4 V ΔV
OUT
, R
L
= 100 Ω
POWER SUPPLY
Operating Range, Single Supply 11.75 12.5 V
Total Quiescent Current Full chip
PD_A = 0, PD_B = 0, PD_PMP = 0 35.6 38 mA Pumps are on, both channels active
PD_A = 0, PD_B = 0, PD_PMP = 1 22.0 25 mA Pumps are off, both channels active
PD_A = 0, PD_B = 1, PD_PMP = 0 21.0 23.5 mA Pumps are on, one channel active
PD_A = 0, PD_B = 1, PD_PMP = 1 10.6 13 mA Pumps are off, one channel active
PD_A = 1, PD_B = 1 2.5 3.5 mA Pumps are off, both channels inactive
20
mV
With respect to midsupply
Threshold
PD_A = 0, PD_B = 0 0.8 V
PD_A = 1, PD_B = 1 2.4 V
Input Current
PD_A = 0, PD_B = 0 35 60 µA
0 0.8 V
PD_A = 1, PD_B = 1 5 10 µA
1 2.4 V
ADLD8403 Data Sheet
Rev. D | Page 4 of 10
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, V
CC
13.2 V
Power Dissipation
See Figure 3
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θ
JA
is specified in still air with the exposed pad soldered to a
4-layer JEDEC test board. θ
JC
is specified at the exposed pad.
Table 3. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
20-Lead LFCSP (CP-20-8) 36.1 5.7 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADLD8403 is
limited by its junction temperature on the die.
The maximum safe junction temperature of plastic encapsulated
devices, as determined by the glass transition temperature of the
plastic, is 150°C. Exceeding this limit may temporarily cause a shift
in the parametric performance due to a change in the stresses
exerted on the die by the package. Exceeding this limit for an
extended period can result in device failure.
Figure 3 shows the maximum power dissipation in the package vs.
the ambient temperature for the 20-lead LFCSP on a JEDEC
standard 4-layer board. θ
JA
values are approximations.
6
0
1
2
3
4
5
–25 857565
55453525155–5–15
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATUREC)
T
J
= 150°C
08848-003
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
for a 4-Layer Board
The power dissipated in the package (P
D
) is easily computed by
taking the total power consumed while driving a signal and
subtracting the power dissipated in the load. The total power
consumed is simply the product of the voltage between the
supply pins (VCC, VEEP, and VCCP) times the supply current (I
S
).
Use rms voltages and currents.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more copper in direct contact with the package leads
from PCB traces, through holes, ground, and power planes
reduces θ
JA
.
ESD CAUTION
Data Sheet ADLD8403
Rev. D | Page 5 of 10
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
VCCP
15
CAPP
GND
VEEP
11
CAPN
INPA
PD_PMP
2
INNA
INNB
5
INPB
7
PD_B
6
VCOM_B
8
VONB
9
VOPB
10
GND
19
PD_A
20
VCOM_A
18
VONA
17
VOPA
16
VCC
ADLD8403
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD TO THE GND PLANE FOR
THE THERMAL PATH. NO INTERNAL ELECTRICAL
CONNECTION EXISTS.
08848-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 INPA Port A Input P
2 INNA Port A Input N
3 PD_PMP Control for Port A and Port B Pumps
4 INNB Port B Input N
5 INPB Port B Input P
6 VCOM_B Port B V
COM
7 PD_B Port B Shutdown
8
VONB
Port B Output N
9 VOPB Port B Output P
10 GND Ground
11 CAPN Pump Capacitor Negative
12 VEEP Dynamic Negative Supply
13 GND Ground
14 VCCP Dynamic Positive Supply
15 CAPP Pump Capacitor Positive
16 VCC Positive Power Supply
17 VOPA Port A Output P
18 VONA Port A Output N
19
PD_A
Port A Shutdown
20 VCOM_A Port A V
COM
EPAD Exposed Pad. Connect the exposed pad to the GND plane for the thermal path. No internal electrical connection exists.

ADLD8403ACPZ-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Operational Amplifiers - Op Amps Dual port Class H ADSL2+ Line Driver
Lifecycle:
New from this manufacturer.
Delivery:
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