ADLD8403 Data Sheet
Rev. D | Page 8 of 10
APPLICATIONS INFORMATION
SUPPLIES, GROUNDING, AND LAYOUT
The ADLD8403 is powered from a single 12.5 V power supply.
For optimum performance, use a well-regulated low ripple
power supply. As with all high speed amplifiers, pay close
attention to supply decoupling, grounding, and overall board
layout. Provide low frequency supply decoupling by using a
10 µF tantalum capacitor between VCC and ground. In addition,
decouple VCC to ground using a high quality 0.1 µF ceramic
chip capacitor placed as close as possible to the driver. Use an
internal low impedance ground plane to provide a common
ground point for all driver and decoupling capacitor ground
requirements. Whenever possible, use separate ground planes for
analog and digital circuitry.
Do not decouple the pumped supply pins, VCCP and VEEP,
because doing so adversely affects the operation of the internal
charge pumps.
Keep input and output traces as short as possible and as far
apart from each other as practical to minimize crosstalk. Keep
all differential signal traces as symmetrical as possible.
POWER MANAGEMENT
A digitally programmable logic pin switches each port of the
ADLD8403 between active bias and shutdown states. The PD_A
pin controls Port A, and the PD_B pin controls Port B. These
pins can be controlled directly with either 3.3 V or 5 V CMOS
logic using the GND pins as a reference. If left unconnected,
the PD_A and PD_B pins float high, placing the amplifier in
the power-down state. Additionally, for lower output power
applications in which the differential DMT peaks are below
10 V (assuming a supply voltage of 12.5 V), the PD_PMP pin
can be used to turn off the internal charge pumps for additional
power savings. If left unconnected, the PD_PMP pin floats high,
placing the charge pump in the inactive state. In the event that
PD_A and PD_B are both held high, the charge pump is
disabled, regardless of the logic level on PD_PMP. See the
Specifications section for the quiescent current for each of the
available bias states.
DYNAMIC SUPPLIES
The ADLD8403 uses the stored charge of capacitors to provide
the supply boost necessary to pass the peaks of the xDSL signal.
The capacitors are placed between CAPP and VCCP, as well as
between CAPN and VEEP, as shown in Figure 11. The charge
pump capacitors must be 0.47 µF with a minimum dc voltage
rating of 16 V. Using a dielectric X7R capacitor is recommended.
Charging time is critical for proper chip operation because,
depending on the application, peak currents can be large (up
to 250 mA). The system is optimized for signals with occasional
peaks that are much greater than the rms level, such as the DMT
waveform used in xDSL applications. It may not be applicable
for a system processing a periodic sinusoidal waveform with an
amplitude that exceeds the dc supply (VCC) into a heavy load
(<500 Ω).
TYPICAL ADSL/ADSL2+ APPLICATION
In a typical ADSL/ADSL2+ application, a differential line driver
takes the signal from the analog front end (AFE) and drives it
onto the twisted pair telephone line. Referring to the typical
circuit representation in Figure 12, the differential input appears
at V
IN+
and V
IN−
from the AFE, and the differential output is
transformer-coupled to the telephone line at the tip and ring.
The common-mode operating point, generally midway between
the supplies, is set internally and is available at both VCOM_A
and VCOM_B.
VCC
GND
4kΩ
4kΩ
+
–
+
–
V
COM
0.1µF
V
IN+
V
IN–
1:N
TIP
RING
R
m
R
m
08848-018
Figure 12. Typical ADSL/ADSL2+ Application Circuit
