10©2015 Integrated Device Technology, Inc. Revision C, December 8, 2015
8545 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVDS O ut p ut s
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z
T
) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z
0
) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 2 can be used
with either type of output structure. Figure 3, which can also be used
with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination,
it is recommended to contact IDT and confirm if the output structure
is current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
Figure 2. Standard LVDS Termination
Figure 3. Optional LVDS Termination
LVDS
Driver
Z
O
Z
T
Z
T
LVD S
Receiver
LVD S
Driver
Z
O
Z
T
LVD S
Receiver
C
Z
T
2
Z
T
2
11©2015 Integrated Device Technology, Inc. Revision C, December 8, 2015
8545 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8545.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8545 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 52mA = 180.18mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.180W * 66.6°C/W = 97°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resitance
JA
for 20 Lead TSSOP, Forced Convection
JA
by Velocity
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
12©2015 Integrated Device Technology, Inc. Revision C, December 8, 2015
8545 Datasheet
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for 8545 is: 644
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
JA
by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
aaa 0.10

8545BGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1-to-4 LVCMOS/LVTTL- to-LVDS Fanout Buffe
Lifecycle:
New from this manufacturer.
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