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5T9304EJGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Rev A 5/13/15 10 LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5T9304I DATA SHEET
Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
NOTE 1: Pulse skew is calculated using the following expression:
tsk(p) =
|tp
HL
– tp
LH
|
Note that the tp
HL
and tp
LH
shown above ae not valid measurements for this calculation because they are not taken from the same pulse.
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Endable Showing Runt Pulse Generation
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G
signal to avoid this problem.
tPLH
tPHL
tSK(O)
tSK(O)
Qn - Qn
Qm - Qm
+ VDIF
VDIF = 0
- V
DIF
+ VDIF
VDIF = 0
- V
DIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- V
DIF
1/fo
LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 11 Rev A 5/13/15
5T9304I DATA SHEET
Power Down Timing
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to V
DD
. In the Power Down Timing diagram this is
shown when Qn/Qn goes to V
DIF
= 0.
A1 - A1
G
V
THI
VIH
VIL
Qn - Qn
+VDIF
VDIF=0
-V
DIF
+VDIF
VDIF=0
-V
DIF
+VDIF
VDIF=0
-V
DIF
PD
A2 - A2
VTHI
VIH
VIL
Rev A 5/13/15 12 LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5T9304I DATA SHEET
Test Circuit for Differential Input
Table 6A. Differential Input Test Conditions
Symbol V
DD
= 2.5V ± 0.2V Unit
V
THI
Crossing of A and A V
VDD/2
D.U.T.
A
A
Pulse
Generator
~50Ω
Transmission Line
~50Ω
Transmission Line
VIN
VIN
-VDD/2
Scope
50Ω
50Ω
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

5T9304EJGI8

Mfr. #:
Buy 5T9304EJGI8
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1:4 Clock Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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