5T9304EJGI8 Datasheet 5T9304EJGI8, 5T9304EJGI | P7-P9

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 7 Rev A 5/13/15

5T9304I DATA SHEET

Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, V

= 2.5V±0.2V, T

= -40°C to 85°C

NOTE 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)

environment. This device meets the VDIF (AC) specification under actual use conditions.

NOTE 2. A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an

automatic test equipment (ATE) environment. This device meets the V

X specification under actual use conditions.

NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.

NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.

Table 5D. LVDS Differential Input AC Characteristics, T

= -40°C to 85°C

NOTE 1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)

environment. This device meets the VDIF (AC) specification under actual use conditions.

NOTE 2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This

device meets the V

X specification under actual use conditions.

NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.

NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.

Table 5E. AC Differential Input Characteristics

(1)

, V

= 2.5V±0.2V, T

= -40°C to 85°C

NOTE 1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by V

DIF

has been

met or exceeded.

NOTE 2. V

DIF

specifies the minimum input voltage (V

– V

) required for switching where V

is the “true” input level and V

is the

“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.

NOTE 3. V

specified the maximum allowable range of (V

+ V

) /2.

Symbol Parameter Maximum Units

DIF

Input Signal Swing

(1)

732 mV

Differential Input Cross Point Voltage

(2)

LVEPECL 1082 mV

LVPECL 1880 mV

Duty Cycle 50 %

THI

Input Timing Measurement Reference Level

(3)

Crossing Point V

/ t

Input Signal Edge Rate

(4)

2V/ns

Symbol Parameter Maximum Units

DIF

Input Signal Swing

(1)

400 mV

Differential Input Cross Point Voltage

(2)

1.2 V

Duty Cycle 50 %

THI

Input Timing Measurement Reference Level

(3)

Crossing Point V

/ t

Input Signal Edge Rate

(4)

2V/ns

Symbol Parameter Minimum Typical Maximum Units

DIF

AC Differential Voltage

(2)

0.1 3.6 V

Differential Input Cross Point Voltage 0.05 V

Common Mode Input Voltage Range

(3)

0.05 V

Input Voltage -0.3 3.6 V

Rev A 5/13/15 8 LVDS, 1:4 CLOCK BUFFER TERABUFFER™

5T9304I DATA SHEET

Table 5F. AC Characteristics

(1,5)

, V

= 2.5V±0.2V, T

= -40°C to 85°C

NOTE. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.

NOTE 2. Skew measured between Crosspoint of all differential output pairs under identical input and output interfaces, transitions and load

conditions on any one device.

NOTE 3. Skew measured is the difference between propagation delay times tp

and tp

of any differential output pair under identical input

and output interfaces, transitions and load conditions on any one device.

NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,

given identical transitions and load conditions at identical V

DD levels and temperature.

NOTE 5. All parameters are tested with a 50% input duty cycle.

NOTE 6. Guaranteed by design but not production tested.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

tsk(o) Same Device Output Pin-to-Pin Skew

(2)

50 ps

tsk(p) Pulse Skew

(3)

125 ps

tsk(pp) Part-to-Part Skew

(4)

300 ps

Propagation Delay, Low-to-High

A Crosspoint to Qn, Qn

Crosspoint

1.7 1.9 ns

Propagation Delay, High-to-Low 1.7 1.9 ns

fo Frequency Range

(6)

450 MHz

PGE

Output Gate Enable Crossing

VTHI-to-Qn/Qn Crosspoint

3.5 ns

PGD

Output Gate Enable Crossing

VTHI-to-Qn/Qn Crosspoint Driven to

Designated Level

3.5 ns

PWRDN

PD Crossing V

THI

-to-Qn = V

, Qn = V

100 µS

PWRUP

Output Gate Disable Crossing V

THI

Qn/Qn Driven to Designated Level

100 µS

/ t

Output Rise/Fall Time

(6)

20% to 80% 125 700 ps

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 9 Rev A 5/13/15

5T9304I DATA SHEET

Applications Information

EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 1. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadframe Base Package, Amkor Technology.

Figure 1. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

GROUND PLANE

LAND PATTERN

SOLDER

THERMAL VIA

EXPOSED HEAT SLUG

(GROUND PAD)

PIN PAD

SOLDER

PIN PAD

SOLDER

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

5T9304EJGI8

Mfr. #:

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Description:

Clock Buffer 450 MHz 2.5V LVDS 1:4 Clock Buffer

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5T9304EJGI8

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