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5T9304EJGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 13 Rev A 5/13/15
5T9304I DATA SHEET
Test Circuit for DC Outputs and Power Down Tests
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
Table 6B. Differential Input Test Conditions
NOTE 1: Specifications only apply to “Normal Operations” test condition. The T
IA
/E
IA
specification load is for reference only.
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. T
IA
/E
IA
– 644 specifies 5pF between the output pair.
With C
L
= 8pF, this gives the test circuit appropriate 5pF equivalent load.
Symbol V
DD
= 2.5V ± 0.2V Unit
C
L
0
(1)
pF
8
(1,2)
pF
R
L
50
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator
RL
RL
VOS VOD
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator
50Ω
50Ω
Z = 50Ω
Z = 50Ω
SCOPE
C
L
-VDD/2
CL
Rev A 5/13/15 14 LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5T9304I DATA SHEET
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 6. Package Dimensions
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 24
A 1.10
A1 0.05 0.15
A2 0.85 0.90 0.95
b 0.19 0.30
b1 0.19 0.22 0.25
c 0.09 0.20
c1 0.09 0.127 0.16
D 7.70 7.90
E 6.40 Basic
E1 4.30 4.40 4.50
e 0.65 Basic
L 0.50 0.60 0.70
P 5.0 5.5
P1 3.0 3.2
0° 8°
 0.076
bbb 0.10
LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 15 Rev A 5/13/15
5T9304I DATA SHEET
Ordering Information
Table 8. Ordering Information
Device Type Package Process
XXXXX
XX
X
I
EJG
5T9304
-40° to + 85° (Industrial)
TSSOP - Green
2.5V LVDS 1:4 Glitchless Clock Buffer
Terabuffer™ II
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

5T9304EJGI8

Mfr. #:
Buy 5T9304EJGI8
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1:4 Clock Buffer
Lifecycle:
New from this manufacturer.
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