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AD9726BSVZ

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AD9726
Rev. B | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04540-005
2
REXT
3
CLKVDD
4
C
LKGND
7
C
LKGND
6
CLK–
5
CLK+
1
CLKVDD
8
DGND
9
DVDD
10
DB15+
12
DB14+
13
DB14–
14
DB13+
15
DB13–
16
DB12+
17
DB12–
18
DB11+
19
DB11–
20
DBVDD
11
DB15–
59
58
57
54
55
56
60
53
52
REFIO
RESET
CSB
SDO (SYNCALRM)
SDIO
SCLK (SYNCUPD)
FSADJ
DGND
DVDD
51
DB0–
49
DB1–
48
DB1+
47
DB2–
46
DB2+
45
DB3–
44
DB3+
43
DB4–
42
DB4+
DBGND
41
50
DB0+
PIN 1
21
DBGND
22
DB10+
23
DB10–
24
DB9+
25
DB9–
26
DB8+
27
DB8–
28
DCLK_OUT+
29
DCLK_OUT–
30
DBVDD
31
DBGND
32
DCLK_IN+
33
DCLK_IN–
34
DB7+
35
DB7–
36
DB6+
37
DB6–
38
DB5+
39
DB5–
40
DBVDD
80
SPI_DIS
79
ADVDD
78
ADGND
77
ACVDD
76
ACGND
75
AVDD2
74
AGND2
73
AVDD1
72
AGND1
71
IOUTA
70
IOUTB
69
AGND1
68
AVDD1
67
AGND2
66
AVDD2
65
ACGND
64
ACVDD
63
ADGND
62
ADVDD
61
SDR_EN
AD9726
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED TO GROUND FOR ELECTRICAL AND THERMAL PURPOSES.
Figure 7. Pin Configuration
Table 7. Pin Function Descriptions
Pin
No. Mnemonic Description
1 CLKVDD Clock Supply Voltage
2 REXT Sets Data Clock Output Drive
1
3 CLKVDD Clock Supply Voltage
4 CLKGND Clock Supply Common
5 CLK+ DAC Clock Input True
6 CLK− DAC Clock Input Complement
7 CLKGND Clock Supply Common
8 DGND Digital Supply Common
9 DVDD Digital Supply Voltage
10 DB15+ Data Bit 15 True
11 DB15− Data Bit 15 Complement
12 DB14+ Data Bit 14 True
13 DB14− Data Bit 14 Complement
14 DB13+ Data Bit 13 True
15 DB13− Data Bit 13 Complement
16 DB12+ Data Bit 12 True
17 DB12− Data Bit 12 Complement
18 DB11+ Data Bit 11 True
19 DB11− Data Bit 11 Complement
20 DBVDD Data Bus Supply Voltage
21 DBGND Data Bus Supply Common
Pin
No. Mnemonic Description
22 DB10+ Data Bit 10 True
23 DB10− Data Bit 10 Complement
24 DB9+ Data Bit 9 True
25 DB9− Data Bit 9 Complement
26 DB8+ Data Bit 8 True
27 DB8− Data Bit 8 Complement
28 DCLK_OUT+ Data Clock Output True
29 DCLK_OUT− Data Clock Output Complement
30 DBVDD Data Bus Supply Voltage
31 DBGND Data Bus Supply Common
32 DCLK_IN+ Data Clock Input True
33 DCLK_IN− Data Clock Input Complement
34 DB7+ Data Bit 7 True
35 DB7− Data Bit 7 Complement
36 DB6+ Data Bit 6 True
37 DB6− Data Bit 6 Complement
38 DB5+ Data Bit 5 True
39 DB5− Data Bit 5 Complement
40 DBVDD Data Bus Supply Voltage
41 DBGND Data Bus Supply Common
42 DB4+ Data Bit 4 True
AD9726
Rev. B | Page 10 of 24
Pin
No. Mnemonic Description
43 DB4− Data Bit 4 Complement
44 DB3+ Data Bit 3 True
45 DB3− Data Bit 3 Complement
46 DB2+ Data Bit 2 True
47 DB2− Data Bit 2 Complement
48 DB1+ Data Bit 1 True
49 DB1− Data Bit 1 Complement
50 DB0+ Data Bit 0 True
51 DB0− Data Bit 0 Complement
52 DVDD Digital Supply Voltage
53 DGND Digital Supply Common
54 SDO (SYNCALRM) SPI Data Output (SYNCALRM)
2
55 SDIO SPI Data Input/Output
3
56 SCLK (SYNCUPD) SPI Clock Input (SYNCUPD)
4
57 CSB SPI Chip Select Bar (Active Low)
58 RESET Hardware Reset (Active High)
59 REFIO Internal Reference Input/Output
5
60 FSADJ Output Current Full-Scale Adjust
6
61 SDR_EN Single Data Rate Mode Enable
7
62 ADVDD Analog Supply Voltage
63 ADGND Analog Supply Common
64 ACVDD Analog Supply Voltage
65 ACGND Analog Supply Common
66 AVDD2 Analog Supply Voltage
67 AGND2 Analog Supply Common
68 AVDD1 Analog Supply Voltage
Pin
No. Mnemonic Description
69 AGND1 Analog Supply Common
70 IOUTB Analog Current Output Complement
71 IOUTA Analog Current Output True
72 AGND1 Analog Supply Common
73 AVDD1 Analog Supply Voltage
74 AGND2 Analog Supply Common
75 AVDD2 Analog Supply Voltage
76 ACGND Analog Supply Common
77 ACVDD Analog Supply Voltage
78 ADGND Analog Supply Common
79 ADVDD Analog Supply Voltage
80 SPI_DIS Serial Port Interface Disable
8
EPAD
Analog Ground. Serves as an
electrical connection to the
substrate of the die and should be
connected to ground for electrical
and thermal purposes.
1
Nominally 1 kΩ to DBGND (may be omitted if data clock output is unused).
2
SDO is output in 4-wire SPI mode and three-state in 3-wire SPI mode. If SPI is
disabled (SPI_DIS = ADVDD), the alternate pin function is SYNCALRM output.
3
SDIO is input only in 4-wire SPI mode and bidirectional in 3-wire SPI mode.
4
If SPI is disabled (SPI_DIS = ADVDD), the alternate pin function is SYNCUPD.
5
Bypass with 0.1 μF to AGND1. Use the buffer amp to drive external circuitry.
Limit the output current to 1 μA. Apply an external reference to this pin.
6
Nominally 2 kΩ to AGND1 for 20 mA full-scale output (internal reference).
7
If SPI is disabled, tie the pin to ADVDD to enable SDR. Otherwise, tie to
ADGND.
8
Tie the pin to ADVDD to disable SPI; otherwise, tie to ADGND.
AD9726
Rev. B | Page 11 of 24
TERMINOLOGY
Integral Nonlinearity (INL)
The maximum deviation of the actual analog output from the
ideal output, as determined by a straight line drawn from zero
scale to full scale.
Differential Nonlinearity (DNL)
A measure of the maximum deviation in analog output associated
with any single value change in the digital input code relative to
an ideal LSB.
Offset Error
The deviation of the output current from the ideal zero-scale
current. For differential outputs, 0 mA is expected at I
OUTA
when
all inputs are low, and 0 mA is expected at I
OUTB
when all inputs
are high.
Monotonicity
A DAC is monotonic if the analog output increases or remains
constant in response to an increase in the digital input.
Gain Error
The deviation of the output current from the ideal full-scale
current. Actual full-scale output current is determined by
subtracting the output when all inputs are low from the output
when all inputs are high.
Output Compliance Range
The range of allowable voltage seen by the analog output of a
current output DAC. Operation beyond the compliance limits
may cause output stage saturation and/or breakdown resulting
in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change in a
parameter from ambient temperature (25°C) to either T
MIN
or T
MAX
and is typically reported as ppm/°C.
Power Supply Rejection
The maximum change in the full-scale output as all power
supplies are varied over their respective operating voltage range.
Spurious-Free Dynamic Range (SFDR)
The difference in decibels between the peak amplitude of a test
tone and the peak amplitude of the largest spurious signal over
the specified bandwidth.
Intermodulation Distortion (IMD)
The difference in decibels between the maximum peak
amplitude of two test tones and the maximum peak amplitude
of the distortion products created from the sum or difference
of integer multiples of the test tones.
Adjacent Channel Leakage Ratio (ACLR)
The ratio between the measured power of a wideband signal
within a channel relative to the measured power in an empty
adjacent channel.
Noise Spectral Density (NSD)
The measured noise power over a 1 Hz bandwidth seen at the
analog output.
Total Harmonic Distortion (THD)
The ratio in decibels of the rms power sum of the first six
harmonic components to the rms power of the output signal.
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AD9726BSVZ

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Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-Bit 400 MSPS
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