AD9726
Rev. B | Page 17 of 24
THEORY OF OPERATION
The AD9726 uses LVDS for input data to enable high sample
rates and high performance. LVDS technology uses differential
signals for noise rejection and small signal amplitude for fast
speed with lower power. Each LVDS input on the AD9726 has
an internal 100 Ω active load for proper termination.
DAC CLOCK AND DATA CLOCK OUTPUT
The AD9726 uses two clock inputs and offers one clock output.
All are differential signals.
The AD9726 is driven by a master input clock that initiates con-
version and controls all on-chip activity. This signal is referred
to as the DAC clock. It is not LVDS, and the CLK+ and CLK–
pins are high impedance inputs.
The DAC clock is then used to generate the data clock output.
The DCLK_OUT+ and DCLK_OUT– pins form an LVDS
signal that can be used to drive an external FPGA or another
data pump. In SDR mode, the data clock output always runs at
the same frequency as the DAC clock. In DDR mode, the data
clock output always runs at ½ the DAC clock frequency.
Use of the data clock output is optional. It is meant to serve as
a convenient means of regulating the incoming data stream.
The driver can be loaded by a 100 Ω differential termination.
An external 1 kΩ resistor from the REXT pin to DBGND is also
required to set the drive strength. If unused, the data clock
output pins can be left unconnected, and the 1 kΩ resistor at
REXT can be omitted.
The data clock output can also be inverted by asserting the
INVDCLKO bit in SPI Register 0x02, or the driver can be
disabled by asserting the DISDCLKO bit in the same register.
DATA CLOCK INPUT
The remaining clock signal associated with the AD9726 is the
data clock input. This LVDS signal is not optional and must
accompany the 16-bit data bus. The data clock input is used to
latch incoming data into the synchronization (sync) logic.
The data clock input always runs at the same frequency as the
data clock output in both SDR and DDR modes. A logical
inversion can be accomplished by asserting the INVDCLKI bit.
Driving the DAC Clock Inputs
The DAC clock must be precise and spectrally pure to ensure
the highest ac performance. A symmetrical 50% duty cycle
should be maintained at all times.
The CLK+ and CLK– input pins should be driven by a signal
with a common-mode voltage near ½ of CLKVDD. From this
point, peak-to-peak signal amplitude should swing over a range
of at least several hundred millivolts.
04540-012
CLK+
VCC – 2V
MC100LVEP16
VCC = CLKVDD = 2.5V
VBB = 1.0V
1:1
50Ω50Ω
CLK–
AD9726
25Ω
25Ω
Figure 19. Active DAC Clock Drive Circuit
The circuit option shown in Figure 19 uses a receiver/driver IC
from the 2.5 V LVPECL logic family to provide complementary
outputs that fall within these guidelines. A transformer helps
ensure a 50% duty cycle and provides a single-ended to differ-
ential conversion at the input.
The LVPECL device can be conveniently powered from the
same power supply as CLKVDD. The center tap of the trans-
former secondary must be held at 1 V, the switching threshold
of the receiver/driver inputs (use a resistive divider to generate
this voltage or use the internal VBB source with a buffer
amplifier). Based on a 1:1 impedance ratio, 25 Ω resistors across
the secondary provide a matched load to a 50 Ω source.
The driver outputs are terminated as close as possible to the
AD9726 with 50 Ω to VCC − 2 V (or use a Thevenin equivalent
circuit). Controlled impedance PCB traces should be used to
minimize reflections. Signal levels at the CLK+ and CLK– pins
transition between a high near 1500 mV to a low near 750 mV.
0.1μF
0.1μF
04540-013
CLK+
VDC BIAS = 1.25V
1:1
50Ω
CLK–
AD9726
Figure 20. Passive DAC Clock Drive Circuit
An alternative circuit option for driving the DAC clock inputs
employs a transmission line transformer (balun) to accomplish
the single-ended to differential conversion. This all-passive
circuit is considerably simpler and less costly, and it provides
acceptable performance over a limited range of frequencies.
In this implementation, a sine wave (or other single-ended
source) is coupled directly to the differential DAC clock inputs
through a 50 transformer. Capacitors are used for isolation,
and each DAC clock pin must be dc-biased to a level of 1.25 V
(a pair of simple resistive dividers can be used).
