AD9726BSVZ Datasheet AD9726BSVZ, AD9726BSVZRL | P19-P21

AD9726

Rev. B | Page 18 of 24

The 50 Ω termination resistor should be placed as close as pos-

sible to the input pins, and controlled impedance PCB traces

should be used.

Good ac performance can be expected from either the active or

passive DAC clock drive circuit. However, in a passive circuit,

the output slew rate is dependent on the frequency of the input;

whereas an active circuit provides consistently high output slew

rates over a wide range of input frequencies.

DATA SYNCHRONIZATION CIRCUITRY

The high performance of the AD9726 requires maintaining

synchronization between the incoming bits and the DAC clock

used to sample and convert the data. Despite the inherent dif-

ficulty in specifying the phase relationship of the DAC clock

and the LVDS data clock input and the challenge presented by

the high operating speed of the interface, the AD9726 contains

real-time logic to automatically monitor and align the data bus

with the DAC clock.

Whether in SDR or DDR mode, input data is always provided

at the same rate. Furthermore, the rate of incoming data always

equals the frequency period of the DAC clock. The data rate and

the DAC clock must also be frequency locked. To accomplish this,

the primary purpose of the data clock output is to provide a

time base for data that is derived directly from the DAC clock.

The function of the data clock input is to latch incoming data

into the sync block. From there, it is the function of the

synchronization logic to position the data with respect to the

DAC clock for optimal ac performance.

Individual data bits must maintain close alignment with one

another so that PCB traces have matched delays across the

width of the 16-bit bus. In addition, a fixed setup and hold

timing relationship between the data clock input and the data

bus is required.

However, because of the sync logic, the phase relationship between

the data bus and the DAC clock is internally optimized.

Furthermore, if the phase between the data bus and the DAC

clock drifts over time or temperature, the sync logic automat-

ically updates and adjusts for it. After synchronization is

reached, the phase between the data bus and the DAC clock can

vary by a full cycle without loss or corruption of data.

More detailed explanations of sync operation and optional

programmable modes are presented in the

Sync Logic

Operation and Programming section, which also includes an

explanation of how to use the sync logic without the SPI.

Data Synchronization Circuitry Bypass

Due to internal design limitations, the data synchronization

circuitry does not assure a fixed or predictable pipeline delay

between the data input and the analog output after power-up.

For designs where multichip synchronization or fixed pipeline

delay is important, the AD9726 can be configured to bypass the

resynchronization circuitry and assure a fixed pipeline delay of

four DAC clock cycles. In this mode, the data is sampled into

the DAC using the DAC clock (CLK±) and following the timing

presented in Figure 4, Figure 5, and Tabl e 4.

The data synchronization circuitry bypass is enabled by writing

0x40 to Address 0x16. The AD9726 should also be configured

in single data rate mode by writing 0x80 to Address 0x02. In this

mode, the sync logic is bypassed, making its configurations and

status reporting irrelevant.

ANALOG OUTPUT

The AD9726 is based around a high dynamic range CMOS

core. The analog output consists of differential current sources,

each capable of up to 20 mA full scale. Discrete output devices

are PMOS and capable of sourcing current into an output

termination within a compliance voltage range of ±1 V.

In a typical application, both outputs drive discrete resistors-to-

analog ground. From there, especially for higher frequency

outputs, they feed the center-tap secondary of a 1:1 RF trans-

former. A differential-to-single-ended conversion is accomplished

that provides added gain and cancellation of even ordered

harmonics.

25Ω

–

3dB

25Ω

IOUT

IOUTB

04540-021

Figure 21. Transformer Output Circuit

For maximum output power, resistor values can be increased to

50 Ω to provide up to 0 dBm into a 50 Ω load without loss of

performance for most transformers.

04540-011

50Ω

IOUTA

50Ω

IOUTB

NOTES

1. USE RF AND RG TO SET GAIN

AND LIMIT BANDWIDTH

Figure 22. Op Amp Output Circuit

As an alternative, an active output stage can be used in the

classic instrumentation amplifier configuration. Here, each

DAC output feeds the noninverting input of one of the Analog

Devices, Inc., high speed transimpedance op amps.

AD9726

Rev. B | Page 19 of 24

INTERNAL REFERENCE AND FULL-SCALE OUTPUT

The AD9726 contains an internal 1.2 V precision reference

source; this reference voltage appears at the REFIO pin. It can

be used to drive external circuitry if properly buffered.

Apply an external reference voltage source to the REFIO pin if

desired. The internal source is designed to be easily overdriven

by an external source; however, the internal reference can also

be powered down using the EXTREF bit in SPI Register 0x00.

The reference voltage (either internal or external) is applied to

an external precision resistor at the FSADJ pin. The resulting

current is internally amplified to provide the full-scale current

at the DAC output according to the following equation:

OUTFS

= VREF/R

FSADJ

× 32

Taking into account the binary value appearing at the data bus

inputs, the output currents I

OUTA

and I

OUTB

can be determined

according to the following equations:

IOUTA = I

OUTFS

× DB[15:0]/65536

IOUTB = I

OUTFS

× (1 − DB[15:0])/65536

Note that the AD9726 features nonvolatile, factory-calibrated

gain using the internal reference source and a precision 2 kΩ

load. Gain accuracy in any application is, therefore, dependent

upon the accuracy of R

FSADJ

RESET

Following initial power-up and application of a valid DAC clock

signal, the AD9726 should always be initialized with an active

high pulse on the RESET pin. This defaults the programmable

registers, initializes volatile calibration memory, and prepares

the synchronization logic for data. The data bus should be static

prior to the reset pulse. After reset, LVDS data can flow.

The default state of the AD9726 is DDR and twos complement

binary input data. To use the AD9726 in this mode, it is not

necessary to program any device registers. However, the SPI is

enabled by default unless the SPI_DIS pin is connected high. If

not disabled, SPI input pins should not be left floating.

SERIAL PORT INTERFACE

The serial port interface is a flexible and synchronous serial

communications port allowing easy interface to many industry

standard microcontroller and microprocessor protocols

(including both Motorola SPI® and Intel® SSR). The interface

provides read/write access to registers that configure the

operation of the AD9726.

The AD9726 SPI supports single-byte and multibyte transfers as

well as MSB- or LSB-justified data formats. The interface can be

configured in 3-wire mode (in which SDIO is bidirectional) or

the default 4-wire mode (in which SDIO and SDO function as

unidirectional data input and data output, respectively).

Communication Cycle

All communication cycles have two phases. The first phase is

concerned with writing an instruction byte into the SPI

controller and always coincides with the first eight rising edges

of SCLK. The instruction byte provides the controller with

information regarding the second phase of the cycle, namely the

data transfer phase. The instruction byte contains the number

of data bytes to be transferred (one to four), a register address,

and a bit initiating a read or write operation.

04540-010

CSB

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SCL

SDIO

SDO

R/W N1 N0 A4 A3 A2 A1 A0 D7

Figure 23. SPI Communication Cycle

Any communication cycle begins with CSB going low, which

also resets the SPI control logic. Similarly, any communication

cycle ends with CSB going high, which aborts any incomplete

data transfer. After a communication cycle begins, the next

eight SCLK rising edges interpret data on the SDIO pin as the

instruction byte.

Instruction Byte

The instruction byte bits are shown in the following bit map.

B7 B6 B5 B4 B3 B2 B1 B0

R/W

N1 N0 A4 A3 A2 A1 A0

Bit 7 of the instruction byte selects a read or write transfer. If

the bit is set high, a read operation is indicated. If the bit is low,

a write operation is indicated.

N1, N0

Bit 6 and Bit 5 of the instruction byte determine the number of

data bytes to be transferred, as shown in Table 10.

Table 10.

N1 N0 Description

0 0 Transfer one data byte

0 1 Transfer two data bytes

1 0

Transfer three data bytes

1 1 Transfer four data bytes

A4, A3, A2, A1, A0

Bit 4 through Bit 0 of the instruction byte specify a 5-bit binary

value corresponding to a valid register address. In the case of

multibyte transfers, the location specified is either an initial or

a concluding register address. The SPI controller increments

or decrements this value to generate successive address values

depending on whether LSB or MSB justification is active.

AD9726

Rev. B | Page 20 of 24

MSB/LSB Transfers

The SPI can support both MSB- and LSB-justified serial data

byte formats. This functionality is determined by Bit 6 in SPI

In this mode, serial data bits are written to and/or read from

registers sequentially from Bit 7 to Bit 0.

If Bit 6 of SPI Register 0x00 is set high, the controller switches

to LSB justification. In this mode, data bits are written to or

read from registers sequentially from Bit 0 to Bit 7. Writing to

the instruction bytes is also affected by the active justification.

For multibyte transfers with MSB justification, the address in

the instruction byte is interpreted as a final address, and its value

is decremented automatically by the controller. For multibyte

transfers with LSB justification, the address in the instruction

byte is interpreted as an initial address, and its value is incremented

automatically by the controller.

Care must be exercised when switching from MSB to LSB

justification. The controller switches modes immediately once

all eight bits of SPI Register 0x00 are written (even if in the

process of a multibyte transfer). For this reason, a single byte

command is recommended when changing justification.

3-Wire and 4-Wire Operation

Bit 7 of SPI Register 0x00 defaults low, enabling 4-wire SPI

operation. In this mode, serial data is input from the SDIO pin,

and serial data is output on the SDO pin. Setting Bit 7 of SPI

SDIO becomes bidirectional and switches automatically from

input to output when necessary. The SDO pin in this mode is

unused and assumes a high impedance state.

As with MSB or LSB justification, care must be exercised when

switching operational modes. The change occurs immediately

once all eight bits of SPI Register 0x00 are written.

Writing and Reading Register Data

Bringing CSB low initiates a new communication cycle. The

next eight rising edges of SCLK latch data from SDIO into the

instruction byte. If Bit 7 of the instruction byte is low, a write

operation is enabled. If Bit 7 is high, a read operation is enabled.

For a write operation, a data byte is latched from the SDIO pin

into a register on the next eight rising edges of SCLK. If the

instruction byte Bit 6 and Bit 5 are not both 0, a multibyte

transfer latches data bytes into adjacent registers after each

successive set of eight rising SCLK edges. Depending upon

MSB or LSB justification, the controller decrements or

increments the address value in the instruction byte during

the cycle as necessary.

If a read operation is enabled, data bits from the register being

addressed appear on SDO (or SDIO) with each falling edge of

SCLK. Note that for a read operation, the eighth bit of the

instruction byte is latched on the eighth rising edge of SCLK,

and the first output bit is enabled on the immediately following

falling SCLK edge.

For multibyte read sequences, the controller adjusts the register

address when necessary, and subsequent data bit values appear

at the output with each falling SCLK edge.

Disabling the SPI

Tie the SPI_DIS pin high to ADVDD to disable the serial port

inteface. In this state, the default DDR operational mode can be

changed to SDR by pulling the SDR_EN pin high to ADVDD.

In addition, with the SPI disabled, the sync logic no longer oper-

ates in a fully automatic mode. See the Sync Logic Operation

and Programming section for a full explanation of sync opera-

tional modes.

SPI PIN DESCRIPTION

The AD9726 SPI logic runs from the DBVDD supply rail, and

input/output thresholds are based upon a nominal 3.3 V level.

The maximum frequency of operation is 15 MHz.

Chip Select (CSB)

The CSB pin is an active low input. It begins and ends any

communication cycle and must remain low during the entire

cycle. An incomplete cycle is aborted if CSB is prematurely

returned high.

Serial Clock (SCLK)

The SCLK pin is used to synchronize data to and from the SPI

registers, and the controller state machine runs from this input.

It is, therefore, possible to read and write register data (but not

SMEM/FMEM) without a valid DAC clock. All input data is

registered on the rising edge of SCLK, and output data bits are

enabled on the falling edge of SCLK.

Serial Data Input/Output (SDIO)

Data is always written into the SPI on the SDIO pin. In 3-wire

mode, however, data is also driven out using this pin. The

switch from input to output occurs automatically between the

instruction and data transfer phases of a read operation. In the

default 4-wire mode, SDIO is unidirectional and input only.

Serial Data Output (SDO)

Serial data is driven out on the SDO pin when the SPI is in its

default 4-wire mode. In 3-wire mode (or whenever CSB is high),

SDO is set to a high impedance state.

CALIBRATION

To ensure linearity to the 16-bit level, the AD9726 incorporates

132 calibration DACs (CALDACs), which are used to linearize

the current output transfer function. Each CALDAC is a 6-bit

device and takes its input directly from static memory (SMEM).

There are 127 CALDACs associated with each major transition

of the 16-bit input data-word (that is, any transition involving

the upper 7 MSBs). A 128th CALDAC operates on the sum total

of the lower nine LSBs. The remaining four CALDACs (129 to

132) are used to adjust the DAC’s overall transfer function gain.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD9726BSVZ

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Manufacturer:

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Digital to Analog Converters - DAC 16-Bit 400 MSPS

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AD9726BSVZ

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