SI5350A-A-GTR Datasheet SI5350A-A-GT, SI5350A-A-GU, SI5350A-A-GTR | P10-P12

Si5350A

10 Rev. 0.9

4. Configuring the Si5350A

The Si5350A is a factory-programmed custom clock generator that is user definable with a simple to use web-

based utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that

allows the user to enter input and output frequencies along with other custom features as described in the following

sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum

configuration. A unique part number is assigned to each custom configuration.

4.1. Crystal Inputs (XA, XB)

The Si5350A uses a fixed-frequency standard AT-cut crystal as a reference to synthesize its output clocks.

4.1.1. Crystal Frequency

The Si5350A can operate using either a 27 MHz or a 25 MHz crystal.

4.1.2. Internal XTAL Load Capacitors

Internal load capacitors (C

) are provided to eliminate the need for external components when connecting a XTAL

to the Si5350A. Options for internal load capacitors are 6, 8, or 10 pF. XTALs with alternate load capacitance

requirements are supported using external load capacitors <

2 pF as shown in Figure 5.

Figure 5. External XTAL with Optional Load Capacitors

4.2. Output Clocks (CLK0–CLK7)

The Si5350A is orderable as a 3-output (10-MSOP) or 8-output (24-QSOP, 20-QFN) clock generator. Output clocks

CLK0 to CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional

frequency select pins (FS0/1). See “4.3.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the

frequency select pins.

4.2.1. Output Clock Frequency

Outputs can be configured at any frequency from 8 kHz up to 100 MHz. In addition, the device can generate any

frequency up to 160 MHz on two of its outputs.

4.2.2. .Spread Spectrum

Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is

useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its

frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB

Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB.

The Si5350A supports several levels of spread spectrum allowing the designer to choose an ideal compromise

between system performance and EMI compliance.

An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature.

See “4.3.1. Spread Spectrum Enable (SSEN)” for details.

Optional internal

load capacitors

6 pF, 8 pF, 10 pF

Optional additional

external load

capacitors

2 pF)

Si5350A

Rev. 0.9 11

Figure 6. Available Spread Spectrum Profiles

4.2.3. Invert/Non-Invert

By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to

invert any of the clock outputs is also available.

4.2.4. Output State When Disabled

There are up to three output enable pins configurable on the Si5350A as described in “4.3.4. Output Enable

(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as one of the

following: disable low, disable high, or disable in high-impedance.

4.2.5. Powering Down Unused Outputs

Unused clock outputs can be completely powered down to conserve power.

4.3. Programmable Control Pins (P0–P4) Options

Up to five programmable control pins (P0-P4) are configurable allowing direct pin control of the following features:

4.3.1. Spread Spectrum Enable (SSEN)

An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with

spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient

method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.

4.3.2. Power Down (PDN)

An optional power down control pin allows a full shutdown of the Si5350A to minimize power consumption when its

output clocks are not being used. The Si5350A is in normal operation when the PDN pin is held low and is in power

down mode when held high. Power consumption when the device is in power down mode is indicated in Table 2 on

page 4.

4.3.3. Frequency Select (FS_0, FS_1)

The Si5350A offers the option of configuring up to two frequencies per clock output on CLK0-CLK5. This is a useful

feature for applications that need to support more than one clock rate on the same output. An example of this is

shown in Figure 7 where the FS pins selects which frequency is generated from the clock output: F1_0 is

generated when FS is set low, and F2_0 is generated when FS is set high.

Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output

Reduced

Amplitude

and EMI

Down Spread

No Spread

Spectrum

Center

Frequency

Amplitude

Video

Processor

27 MHz

XA XB

CLK0

FS0

Si5350A

74.25

1.001

MHz

Output Frequency Selected

FS0

Bit Level

74.25 MHzF1_0:

F2_0:

74.25

1.001

MHz

Si5350A

12 Rev. 0.9

Up to two frequency select pins are available on the Si5350A. Each of the frequency select pins can be linked to

any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency

selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and

CLK4. Any other combination is also possible.

The Si5350A uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock

always completes its last cycle before starting a new clock cycle of a different frequency.

Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)

4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)

Up to three output enable pins (OEB_0/1/2) are available on the Si5350A. Similar to the FS pins, each OEB pin can

be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,

and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and

CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin

forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.

The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading

edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its

full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is

configurable as disabled high, disabled low, or disabled in high-impedance.

Figure 9. Example Configuration of a Pin-Controlled Output Enable

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

FS_0

FS_1

FS_0

F1_0, F1_3, F1_5

F2_0, F2_3, F2_5

Output Frequency

FS_1

F1_1, F1_2, F1_4

Output Frequency

CLKx

Frequency_A Frequency_B

Full cycle completes before

changing to a new frequency

Frequency_A

New frequency starts

at its leading edge

Glitchless Frequency Changes

Cannot be controlled

by FS pins

Customizable FS Control

F2_1, F2_2, F2_4

MultiSynth 0

MultiSynth 1

MultiSynth 2

MultiSynth 3

MultiSynth 4

MultiSynth 5

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

OEB_0

OEB_1

OEB_0

CLK Enabled

CLK Disabled

Output State

OEB_2

OEB_1

CLK Enabled

CLK Disabled

Output State

OEB_2

CLK Enabled

CLK Disabled

Output State

Clock continues until

cycle is complete

CLKx

OEBx

Clock starts on the

first leading edge

Glitchless Output Enable

Customizable OEB Control

OEB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

SI5350A-A-GTR

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IC CLK GEN PLL BLANK CUST 10MSOP

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