Expand menu
Hello, Sign in
My Account
0
Cart
Home
Products
Sensors
Semiconductors
Passive Components
Connectors
Power
Electromechanical
Optoelectronics
Circuit Protection
Integrated Circuits - ICs
Main Products
Manufacturers
Blog
Services
About OMO
About Us
Contact Us
Check Stock
SI5350A-A-GTR
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P22
Si5350A
Rev. 0.9
7
2. T
y
pical Application
2.1. Si5350A Replaces Mu
ltiple Clocks and XOs
The Si5350A is a u
ser-definable cu
stom clock gene
rator that is ideally
suited for replac
ing crystals and crystal
oscillators in cost-sensitive applicatio
ns. An example application is shown
in
Figure 1.
Figure 1. Example of an Si5350A in an Audi
o/Video Application
2.2. Replacing a Cr
ystal with a Clock
The Si5350A can be driven with a clock signal throug
h the XA input pin.
Figure 2. Si5350A Driven by a Clock Signa
l
Video
Processor
Audio
Processor
74.25 MHz or
74.25
1.001
MHz
24.576 MHz
27 MHz
HDMI
Port
22.5792 MHz
Ethernet
PHY
USB
Controller
28.322 MHz
48 MHz
125 MHz
CLK4
CLK0
27 MHz
XA
XB
CPU
33.3333 MHz
CLK1
CLK3
CLK7
CLK6
CLK2
CLK5
Si5350A
Multi
Synth
N
Multi
Synth
0
Multi
Synth
1
PLLB
PLLA
XA
XB
OSC
V
IN
= 1 V
PP
25/27 MHz
Note: Flo
at the XB input
while dri
ving
the XA input
with a clock
0.1 µF
Si5350A
8
Rev. 0.9
2.3. HCSL Comp
atible Output
s
The Si5350A can be configured to support HCSL comp
atible
swing when the VDDO of the output pair of inter
est is
set to 2.5 V (i
.e., VDDOA must be 2.5 V whe
n using CLK0/1; VDDOB must be 2.5 V
for CLK2/3 and so on).
The circuit in the figu
re below must be applied to each
of the
two clocks used, and one of the clocks in the p
air
must also be inverted to generate a dif
ferential pair
.
Figure 3. Si5350A Output is HCSL Comp
atible
Multi
Synth
N
Multi
Synth
0
Multi
Synth
1
PLLB
PLLA
OSC
Note: The c
omplementa
ry -1
80 degree
out of phase
output cloc
k is genera
ted
using the INV function
R
1
511
240
R
2
Z
O
= 70
0
HCSL
CLKIN
R
1
511
240
R
2
Z
O
= 70
0
Si5350A
Rev. 0.9
9
3. Functional Description
The Si5350A
’s synthesis architecture consists of two hi
gh-frequency PLLs in ad
dition to one high-resolution
fractional MultiSynth
TM
divider per
output. A block diagram of both t
he 3-output and 8-
output versions are shown in
Figure
4. This unique architecture allows the Si5350
A to generate up to eig
ht independent, non-integer-
related
frequencies at any of its output
s. Each MultiSynth
TM
is configurable with two frequencies
(F1_x, F2_x). This allows
a pin controlled glitchless frequen
cy c
hange at each output (CL
K0 to CLK5).
Figure 4. Block Diagrams of 3-Output and 8-Output Si5350A Devices
10-MSOP
MultiS
ynth 3
F1_2
F2_2
R2
FS
MultiS
ynth 2
VDD
GND
CLK2
F1_0
F2_0
R0
FS
MultiS
ynth 0
F1_1
F2_1
R1
FS
MultiS
ynth 1
CLK0
CLK1
VDDO
PLL
A
PLL
B
OSC
XA
XB
F1_3
F2_3
R3
FS
MultiS
ynth 3
F1_2
F2_2
R2
FS
MultiS
ynth 2
20-QFN, 24-QSOP
PLL
A
PLL
B
VDD
GND
CLK2
CLK3
VDDOB
Control
Logic
P2
P3
P4
P0
P1
F1_0
F2_0
R0
FS
MultiS
ynth 0
F1_1
F2_1
R1
FS
MultiS
ynth 1
CLK0
CLK1
VDDOA
R6
R7
CLK6
CLK7
VDDOD
F1_4
F2_4
R4
FS
MultiS
ynth 4
F1_5
F2_5
R5
FS
MultiS
ynth 5
CLK4
CLK5
VDDOC
F1_6
MultiSyn
th 6
F1_7
MultiSynth 7
OSC
XA
XB
Control
Logic
P0
P1
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P22
SI5350A-A-GTR
Mfr. #:
Buy SI5350A-A-GTR
Manufacturer:
Silicon Labs
Description:
IC CLK GEN PLL BLANK CUST 10MSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
Paypal
Visa
MoneyGram
Western
Union
Products related to this Datasheet
SI5350A-A-GT
SI5350A-A-GU
SI5350A-A-GTR
SI5350A-A-GUR
